DAC Serializer Randomization for Unit Cell Mismatch Reduction
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Solution Overview
Problem
Existing digital-to-analog converter (DAC) circuits face challenges in improving the quality of analog signals due to mismatch between unit cells, particularly at high resolution and high speed.
Innovation Solution
A DAC circuit that incorporates a serializer circuit with multiplexers, a pseudo random number generation circuit, and switch circuits to generate codes with different random numbers, applied through the switch circuits to improve the randomness and quality of the analog signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional DAC circuit uses a current array with multiple unit cells for high resolution and high speed operation, then the conversion speed and resolution are improved, but mismatch between unit cells degrades the quality of the analog output signal
Solution Approach 1:
The patent applies dynamic element matching (DEM) technique that dynamically switches between different unit cells based on randomly selected codes. The switch circuits change the mapping between digital codes and unit cells in real-time, transforming the static mismatch problem into a dynamic solution where randomization averages out the mismatch effects over time, improving analog signal quality while maintaining high-speed operation
Solution Approach 2:
The patent changes the parameter of code assignment by applying random number generation to the digital codes before they reach the unit cells. By modifying the code parameters through randomization and using switch circuits to implement different code mappings, the system transforms fixed mismatch patterns into randomized variations that average out, reducing their harmful effects on output quality
2Manufacturing precision
If random number generation circuits and switch circuits are added to apply dynamic element matching, then the mismatch between unit cells is reduced and signal quality is improved, but the circuit complexity increases
Solution Approach 1:
The patent segments the code generation process into multiple stages: original code generation, random number generation, and switch circuit selection. By dividing the DAC circuit into distinct functional blocks (serializer, random number generator, switch circuits, unit cells), each component can be optimized independently, managing overall complexity through modular design while achieving dynamic element matching
Solution Approach 2:
The patent introduces random number generation circuits and switch circuits as intermediary components between the digital input and the unit cells. These intermediaries transform the direct code-to-unit-cell mapping into an indirect, randomized mapping process, reducing the impact of unit cell mismatch without requiring changes to the unit cells themselves
3Manufacturing precision
If multiple switch circuits are connected between multiple multiplexers to apply different random numbers, then the randomness and quality of analog signals are improved, but the power consumption increases
Solution Approach 1:
The patent applies partial randomization by using multiple switch circuits at different stages of the serializer rather than randomizing all codes uniformly. By applying dynamic element matching selectively at multiple points in the signal path, the system achieves improved linearity and randomness while distributing the power consumption across multiple lower-power switch circuits rather than one high-power circuit
Data Source
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AI summary
A digital-to-analog converter (DAC) circuit is provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo random number generation circuit configured to generate random numbers in response to edges of a first clock signal; a first switch circuit connected to a first multiplexer; a second switch circuit connected to a second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively.