DAC Shuffling Encoder With Minimum Output Configurations

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Integrated circuits (ICs) built using semiconductor materials face challenges in reducing surface area, power consumption, and complexity, particularly in digital-to-analog converters (DACs), which are proportional to the number of devices used.

Innovation Solution

Implement a shuffling encoder, or dynamic-element matching (DEM) encoder, to parse digital inputs into random bits and drive 1-bit DACs with a minimum number of output configurations, ensuring linearity while minimizing the number of semiconductor components and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of converters in a DAC is increased to improve conversion precision and reduce noise, then the manufacturing cost, power consumption, complexity, and surface area increase proportionally

Engineering Contradiction:
Improveconversion precisionVSAvoidnumber of devices
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the digital input signal into multiple individual bits and processes them through separate 1-bit converters. Each converter handles a specific bit position, and the outputs are combined to achieve the overall conversion precision. This segmentation allows the system to achieve high precision without requiring a single complex multi-bit converter, thereby reducing the number of devices needed while maintaining conversion accuracy.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If the number of converters is reduced to decrease surface area and cost, then the conversion precision and linearity deteriorate

Engineering Contradiction:
Improvesurface areaVSAvoidconversion precision
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent introduces dynamic element matching (DEM) that dynamically assigns different weights to different 1-bit converters based on the input signal characteristics. The shuffling encoder randomly permutes the mapping between input bits and converters, creating a dynamic weighting scheme that maintains linearity and precision. This dynamic approach allows the system to achieve high conversion precision with fewer converters by optimally utilizing each converter's contribution based on the instantaneous signal requirements.

Inventive Principle:
Principle #15Dynamics

3Reliability

If more converters are used to improve linearity and reduce noise, then power consumption increases

Engineering Contradiction:
ImprovelinearityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the operational parameters of the converters by implementing random weight assignment through the shuffling encoder. Instead of using fixed-weight converters that would require multiple high-precision devices, the system uses 1-bit converters with dynamically changed weights achieved through random permutation. This parameter change allows the system to achieve high linearity and low noise performance with fewer, lower-power converters, as the random weighting distributes the precision requirements across multiple time instances rather than requiring simultaneous high precision from multiple devices.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12438549B2Apparatuses and methods for efficient shuffling in a digital to analog converter
Publication Date: 2025.10.07 ANALOG DEVICES INC
  • US12438549B2 patent drawing
  • US12438549B2 patent drawing
  • US12438549B2 patent drawing

AI summary

Aspects of the present disclosure include receiving a digital input signal having an identified value, determining a number of a plurality of converters, determining, based on the identified value and the number, a minimum number of one or more minimum output configurations, parsing the digital input into a plurality of individual bits, and transmitting the plurality of individual bits to the plurality of converters based on an output configuration of the one or more minimum output configurations.