DAC Cell Skew Measurement Using TDC-Based Timing Correction
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Solution Overview
Problem
Current digital-to-analog converters (DACs) face performance limitations due to timing skew errors, which are not effectively corrected and become significant at higher sampling and signal frequencies, impacting linearity and noise.
Innovation Solution
The implementation of a time-to-digital converter (TDC) within the DAC to measure timing skew errors on a per-cell basis, allowing for the generation of correction signals to mitigate these errors, thereby improving DAC performance without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device size is increased to improve matching and reduce random skew errors, then skew error performance is improved, but area and power dissipation increase
Solution Approach 1:
The patent replaces physical scaling of DAC cells with a measurement and correction system. A time-to-digital converter (TDC) measures timing skew errors, and a correction DAC generates compensating signals to cancel these errors. This substitution of physical enlargement with active correction resolves the contradiction by achieving low skew errors without increasing device area.
Solution Approach 2:
The patent implements a feedback loop where the TDC continuously measures timing skew errors from the DAC cells, and the correction DAC applies compensating signals based on these measurements. This feedback mechanism dynamically corrects skew errors without requiring larger device sizes, resolving the contradiction between skew error performance and area.
2Reliability
If device size is increased to improve matching and reduce random skew errors, then skew error performance is improved, but power dissipation increases
Solution Approach 1:
The patent replaces power-intensive physical scaling with a measurement and correction architecture. The TDC and correction DAC consume less power than would be required to scale up all DAC cells for improved matching, resolving the contradiction between skew error performance and power dissipation.
Solution Approach 2:
The patent uses a separate correction DAC that generates compensating signals based on measured errors, rather than physically enlarging the main DAC cells. This copying approach achieves the desired performance with lower power consumption compared to scaling the entire DAC structure.
3Device complexity
If timing skew errors are not corrected, then device complexity is reduced, but DAC performance deteriorates at higher sampling and signal frequencies
Solution Approach 1:
The patent introduces a TDC as an intermediary measurement device and a correction DAC as an intermediary correction device. These intermediaries enable skew error correction without fundamentally redesigning the main DAC structure, achieving high performance at high frequencies while maintaining relatively simple device architecture.
Solution Approach 2:
The patent separates the DAC into main DAC cells for signal conversion and a correction DAC for skew error compensation. This segmentation allows each component to be optimized independently, achieving high performance without excessive overall complexity.
Data Source
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Figure 3A~3B
AI summary
Method and apparatus for skew error measurement and correction in a digital-to-analog converter (DAC) using a time-to-digital converter (TDC). A DAC includes a main DAC and a TDC. The main DAC includes a plurality of DAC cells. The main DAC is configured to generate an analog output signal based on digital input data. The TDC is coupled to an output of the main DAC and configured to measure a timing error of the main DAC. The timing error may be measured on a DAC cell basis or a subset of DAC cells basis.