DAC Switch Bias Circuit for Resistance Tracking and Linearity
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Solution Overview
Problem
Prior art R-2R ladder DACs face significant variations in switch resistance due to bias conditions and temperature, leading to undesirable linearity and glitch settling issues, particularly in VOUT mode DACs, requiring a wide range of switch resistance values that are difficult to fabricate accurately.
Innovation Solution
The use of N-channel switches at REFLO and P-channel switches at REFHI, both biased to track a single thin film resistance, reduces sensitivity to Vref, VDD, and temperature variations, allowing for balanced switch resistance and improved linearity by eliminating the need for a wide range of switch resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a wide range of switch resistance values is used in R-2R ladder DACs, then the DAC can operate in VOUT mode with extended VREF range, but switch resistance variations due to bias conditions and temperature cause undesirable linearity and glitch settling issues
Solution Approach 1:
The patent changes the biasing parameters of the switches by introducing separate gate voltage controls (VGPH for P-channel, VGNL for N-channel) instead of using a single bias voltage. This allows independent optimization of switch resistance characteristics for both P-channel and N-channel switches, compensating for process variations and temperature effects while maintaining a narrow resistance ratio range, thereby improving linearity without sacrificing VREF range
Solution Approach 2:
The patent implements feedback mechanisms through resistive dividers (R1-R4) that sense the actual switch resistance values and adjust the gate voltages accordingly. This feedback loop compensates for temperature drift and process variations, maintaining stable switch resistance ratios over time and across operating conditions, thus resolving the linearity issue while preserving extended VREF range capability
2Device complexity
If N-channel switches are used at both REFHI and REFLO with approximately the same VGS (ON), then the circuit is simplified, but it requires considerable headroom from Vref to VDD and limits the VREF range
Solution Approach 1:
The patent segments the switch control into separate P-channel switches at REFHI and N-channel switches at REFLO, each with independent gate voltage control. This segmentation allows each transistor type to be optimized for its specific voltage domain, enabling extended VREF range operation while maintaining manageable circuit complexity through systematic design of the biasing network
Solution Approach 2:
The patent creates a universal biasing architecture where the resistive divider network and op-amp-based control circuits serve multiple functions: they generate the appropriate gate voltages for both P-channel and N-channel switches, provide temperature compensation, and maintain resistance matching across different operating conditions. This multi-functional approach enables extended VREF range without proportionally increasing circuit complexity
3Ease of manufacture
If switch resistance matching is achieved by scaling N-channel widths, then all switches can be biased at the same voltage, but significant variations in switch resistance occur due to bias conditions and temperature
Solution Approach 1:
The patent changes the control parameter from fixed geometric scaling to dynamic electrical parameter adjustment. Instead of relying solely on fixed width ratios to maintain resistance matching, the patent uses variable gate voltages (controlled by temperature-compensated bias circuits) to actively maintain stable switch resistance values across temperature and bias conditions, significantly improving reliability while keeping fabrication simple
Solution Approach 2:
The patent implements feedback through resistive sensing networks that monitor switch resistance values and adjust gate voltages to compensate for temperature drift and process variations. This closed-loop control maintains stable switch resistance ratios over time and across operating conditions, resolving the reliability issue while preserving ease of manufacture through standard CMOS processes
Data Source
AI summary
A switch signal generator circuit that may form part of a digital to analog converter is provided. The switch signal generator circuit may include a first switch that controls a high reference gate voltage. The high reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a high reference voltage to the digital to analog converter. The switch signal generator circuit may include a second switch that controls a low reference gate voltage. The low reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a low reference voltage to the digital to analog converter. The switch signal generator circuit may also include a resistor. In one embodiment of the invention, a current conducted by the first switch and/or a current conducted by the second switch may each be proportional to a current conducted by the resistor. One of the switches in the switch generator circuit may be a P channel switch. One may be an N channel switch. In one embodiment of the invention, current conducted by the first switch may be proportional to the current conducted by the second switch. Also the current conducted by the first switch may be proportional to temperature.