DAC Switch-Network Self-Test for Faster Production Testing
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Solution Overview
Problem
The testing of digital to analog (DAC) circuits in integrated circuits is cumbersome and costly due to the high number of tests required as the number of bits increases, leading to significant test time and manufacturing costs.
Innovation Solution
A testing system that separates the testing of circuit components and the multiplexing network within the DAC, using a built-in self-test (BIST) sequence to verify the functionality of the multiplexing network without external instrumentation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of bits in the DAC increases to improve resolution and accuracy, then the measurement precision is improved, but the test time increases exponentially due to the huge number of input codes (2^n) that need to be tested
Solution Approach 1:
The patent segments the test process into two distinct phases: (1) a comprehensive test of all 2^n input codes to verify DAC linearity and accuracy, and (2) a focused self-test of the multiplexing network using only 2n test patterns. This segmentation allows the time-consuming comprehensive test to be performed once during manufacturing, while subsequent production testing uses the efficient self-test mode, thereby resolving the contradiction between thorough testing and test time.
Solution Approach 2:
The patent implements a self-test mechanism where the DAC uses its own output to generate test patterns for verifying the multiplexing network functionality. The DAC output is fed back through the multiplexing network and compared with expected values generated by an on-chip logic unit, eliminating the need for external test equipment and reducing test time significantly while maintaining verification accuracy.
2Reliability
If external automatic test equipment is used to test all possible input codes, then the reliability of defect detection is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a self-test mechanism where the DAC uses its own output to generate test patterns for verifying the multiplexing network functionality. The DAC output is fed back through the multiplexing network and compared with expected values generated by an on-chip logic unit, eliminating the need for external test equipment and reducing test time significantly while maintaining verification accuracy.
Solution Approach 2:
The patent extracts the test functionality from external equipment and integrates it directly into the DAC circuit itself. By moving the test logic, pattern generation, and comparison functions onto the chip, the system eliminates dependency on complex external test equipment, thereby reducing device complexity and manufacturing cost while preserving defect detection reliability.
3Reliability
If a comprehensive test of all input codes is performed to detect silicon defectivity, then the reliability is improved, but the productivity decreases due to the huge number of tests required
Solution Approach 1:
The patent segments the test process into two distinct phases: (1) a comprehensive test of all 2^n input codes to verify DAC linearity and accuracy, and (2) a focused self-test of the multiplexing network using only 2n test patterns. This segmentation allows the time-consuming comprehensive test to be performed once during manufacturing, while subsequent production testing uses the efficient self-test mode, thereby resolving the contradiction between thorough testing and test time.
Solution Approach 2:
The patent applies partial action by performing a reduced set of tests (2n patterns instead of 2^n patterns) for routine production testing of the multiplexing network. This partial testing approach is sufficient for detecting manufacturing defects in the switching network while dramatically improving productivity, with the understanding that comprehensive DAC characterization is performed separately during initial manufacturing validation.
Data Source
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AI summary
A system for testing comprising an electronic circuit to be tested (11; 11'; 11"; 11‴) and an automatic testing equipment (12; 12'), said electronic circuit (11; 11'; 11"; 11‴) to be tested comprises a digital to analog converter (111; 111';111"), comprising a set of electronic components (R; I), in particular arranged in a network, coupled to an analog reference voltage or to an analog reference current and a multiplexing network of switches (111b) coupled to said set of electronic components (R;I) and configured to select paths in said set of electronic components (R;I) on the basis of digital values (DC) at the input of said digital to analog converter (111; 111';111") supplied by a logic control module (112) comprised in said electronic circuit (11; 11'; 11"; 11‴), said electronic circuit (11; 11'; 11"; 11‴) to be tested comprising an input data link (113b, 123b) between the automatic testing equipment (20, 20', 20") and the logic control module (112), the system for testing being configured to perform a test of the set of electronic components (R;I) in which the automatic testing equipment (20, 20', 20") is configured to send digital data (TD) to control the logic module (112) inputting digital codes (DC) in the digital to analog converter (111; 111';111") and measuring the analog output of the digital to analog converter (111; 111';111") by a measuring instrument (122; 122') in said automatic testing equipment (12;12') coupled to an output (VDAC, Vin) of the electronic circuit (10, 10', 10‴), then checking if the measured values matches expected converted values for the given digital data (TD), wherein said test of the digital to analog converter (111; 111'; 111") comprises a further test of the multiplexing network of switches (111b) in which said logic module (112) is configured to execute a built-in test sequence (300) comprising supplying by said logic module (112) a sequence of digital codes (DC) forcing given switches of said multiplexing network of switches (111b) in a determined open or close state, said electronic circuit (11'; 11"; 11‴) comprising a feedback circuit (111d) to supply a feedback signal (FB) to said logic module (112), said logic module (112) being configured, on the basis of said feedback signal (FB), to control an execution flow of the built-in test sequence (300)) and to verify (324, 325) if the feedback signal (TB) matches an expected value for the corresponding digital code (DC) in the sequence of digital codes.