Resistor Ladder DAC Switching to Reduce DNL and Leakage
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Solution Overview
Problem
Existing Digital to Analog Converter (DAC) circuits suffer from significant differential non-linearity due to leakage current, leading to inaccurate signal conversion and high power consumption, as they often require numerous switch flips to produce analog voltages, which increases power usage.
Innovation Solution
The implementation of a DAC circuit with two or more levels of switches and corresponding decoder circuits, where overlapping subsets of digital input bits minimize switch flips, reducing leakage current and power consumption while maintaining signal accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DAC circuits use numerous switch flips to produce analog voltages, then signal conversion is achieved, but power consumption increases and leakage current increases
Solution Approach 1:
The patent divides the switch control into multiple levels (first level decoder circuitry and second level decoder circuitry), where each level handles a subset of digital input bits. This segmentation reduces the total number of switch flips required at any given time, thereby reducing power consumption and leakage current while still achieving accurate signal conversion.
2Measurement precision
If conventional DAC circuits use numerous switch flips to produce analog voltages, then signal conversion is achieved, but differential non-linearity increases
Solution Approach 1:
The patent divides the switch control into multiple levels (first level decoder circuitry and second level decoder circuitry), where each level handles a subset of digital input bits. This segmentation reduces the total number of switch flips required at any given time, thereby reducing power consumption and leakage current while still achieving accurate signal conversion.
3Use of energy by moving object
If multi-level decoder circuitry with overlapping subsets is implemented, then switch flips are minimized and power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent divides the switch control into multiple levels (first level decoder circuitry and second level decoder circuitry), where each level handles a subset of digital input bits. This segmentation reduces the total number of switch flips required at any given time, thereby reducing power consumption and leakage current while still achieving accurate signal conversion.
Data Source
AI summary
An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.