Differential DAC Switching Circuit for Low-Distortion Timing
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Solution Overview
Problem
High-speed digital-to-analogue converters (DACs) face issues with third-order distortion due to parasitic capacitances and timing mismatches, which are exacerbated by miniaturization and reduced supply voltages, leading to increased distortion and power consumption.
Innovation Solution
The proposed solution involves a differential switching circuit with four FETs per output node, operating in a series of four phases with complementary clock signals, and a modified switch driver circuit using time-interleaved data signals and mask signals to reduce the impact of parasitic capacitances and timing variations, along with the use of NMOS data-controlled switches to maintain low on-resistance over the entire clock swing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturization and reduced supply voltages are used in high-speed DACs, then device size and power consumption are reduced, but third-order distortion increases due to parasitic capacitances and timing mismatches
Solution Approach 1:
The switching circuit is divided into multiple independent switching units, each handling a portion of the digital input bits. Each unit contains its own set of switches and current sources, allowing independent optimization and reducing the cumulative effect of parasitic capacitances in a single large circuit. This segmentation maintains compact size while reducing distortion through modular architecture.
Solution Approach 2:
The patent optimizes switching parameters including clock signal timing, switch transition rates, and bias currents to compensate for parasitic effects. By carefully controlling the timing parameters of switch activation and deactivation, the circuit minimizes glitch impulses and third-order distortion while maintaining miniaturized dimensions and low supply voltage operation.
2Use of energy by stationary object
If miniaturization and reduced supply voltages are used in high-speed DACs, then device size and power consumption are reduced, but timing mismatches increase leading to increased distortion
Solution Approach 1:
The circuit employs periodic clock signals with optimized duty cycles and frequencies to drive the switching operations. By using synchronized periodic clocking across all switching units, the patent ensures consistent timing behavior that reduces mismatches while maintaining low power consumption through efficient switching rhythms that minimize transition overhead.
Solution Approach 2:
The patent incorporates timing calibration mechanisms that use feedback from actual switching behavior to adjust clock phases and durations. This feedback system compensates for process variations and parasitic effects that cause timing mismatches, ensuring accurate switching timing even in miniaturized low-voltage operation.
3Device complexity
If conventional switching circuits are used with parasitic capacitances, then circuit simplicity is maintained, but glitch impulses increase during input word changes
Solution Approach 1:
The circuit performs preliminary switching actions before the main data transition occurs. Pre-charging and pre-discharging of parasitic capacitances through dedicated switch paths prepares the circuit state in advance, preventing large glitch impulses when the actual data switching occurs. This preliminary action reduces distortion while maintaining relatively simple circuit architecture.
Solution Approach 2:
The patent introduces intermediate switching stages and buffer elements that mediate between the input data changes and the output current switching. These intermediary components provide controlled transition paths that manage parasitic capacitance discharge/charge sequences, reducing glitch impulses without requiring complete circuit redesign.
Data Source
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AI summary
Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.