Current-Steering DAC Timing Skew Measurement Without High-Res ADCs
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Solution Overview
Problem
Current technologies for timing error measurement in current steering digital to analog converters (DACs) face challenges in achieving precise timing alignment, leading to harmonic distortion and requiring complex and costly high-resolution ADCs for correction.
Innovation Solution
A timing error measurement system using a digital-to-analog converter (DAC) with a one-bit comparator, filter, control logic, and delay line, which delays the clock signal to detect timing skews between current steering circuits without needing a mixer or high-resolution ADC, allowing for digital code representation of time delays and scalable correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a mixer and high-dynamic range ADC are used to measure timing errors, then measurement precision is improved, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent uses a simplified measurement system that copies the essential function of timing error detection without requiring a full high-dynamic range ADC. By using a one-bit comparator with delay line-based dithering, the system creates a simplified copy of the measurement capability that achieves adequate precision for timing error correction.
Solution Approach 2:
The patent replaces expensive, complex high-dynamic range ADC hardware with a much simpler one-bit comparator and digital delay line system. This substitution uses inexpensive components that can be easily manufactured and integrated, eliminating the need for costly dedicated measurement hardware while still providing functional timing error measurement capability.
2Reliability
If dynamic element matching with unit scrambling is used, then linearity is improved, but the technique only transforms non-linearity into noise without actually correcting timing errors
Solution Approach 1:
The patent implements a feedback mechanism where timing errors are measured using the one-bit comparator and delay line system, then the measured timing error information is used to adjust or correct the current steering operations. This closed-loop feedback actually corrects the timing errors rather than merely transforming them into noise.
Solution Approach 2:
The patent performs preliminary measurement of timing errors using the simplified comparator-based system before executing the actual DAC conversion. By measuring and correcting timing errors in advance, the system prepares the current steering circuits to operate with proper timing alignment, preventing distortion before it occurs.
3Measurement precision
If high-resolution ADCs are designed for timing error measurement, then measurement precision is improved, but design time and development effort increase dramatically
Solution Approach 1:
The patent replaces the complex analog measurement system (mixer and high-resolution ADC) with a digital-based measurement approach using a one-bit comparator and programmable delay line. This substitution moves the measurement function from the analog domain to the digital domain, where timing can be controlled and measured with high precision using standard digital circuits and software algorithms.
Solution Approach 2:
The patent changes the measurement approach from requiring high-resolution voltage measurement (analog domain) to using timing-based measurement with a one-bit comparator (digital domain). By changing the measurement parameter from voltage amplitude to timing coincidence detection, the system achieves adequate precision without requiring complex high-resolution ADC hardware.
Data Source
AI summary
An example timing error measurement system includes a digital-to-analog converter (DAC) having a plurality of current steering circuits, the DAC responsive to a clock signal, a one-bit comparator coupled to a differential output of the DAC, a filter coupled to an output of the one-bit comparator, control logic coupled to an output of the filter, and a delay line coupled to an output of the control logic. An output of the delay line is coupled to an input of the one-bit comparator. The delay line is configured to delay the clock signal.