DAC Cell Timing Calibration Using a VCO ADC Mixer
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Solution Overview
Problem
Timing mismatch among DAC cells introduces errors in ADCs, degrading the signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) performances, particularly in high-speed ADCs, due to harmonic distortions and dynamic errors.
Innovation Solution
A technique involving a mixer to downconvert timing errors to DC using a VCO ADC, with measurements taken using quadrature phase signals to extract and correct timing errors, which can be implemented in the digital or analog domain, and integrated within a voltage-to-current converter of the VCO ADC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed ADC operation is implemented, then conversion speed is improved, but timing mismatch errors increase degrading SNDR and SFDR performance
Solution Approach 1:
The patent applies preliminary action by performing DAC timing error measurement and calibration before the actual high-speed ADC conversion operation. The error measurement is conducted in a preliminary stage using test signals, and the measured timing errors are stored and compensated during subsequent normal operation, thus preventing performance degradation before it occurs.
Solution Approach 2:
The patent implements feedback by measuring the actual timing errors of DAC cells using test signals and quadrature phase signals, then using these measured error values to compensate for timing mismatches during normal ADC operation. The system continuously monitors and corrects timing errors, creating a closed-loop feedback mechanism that maintains high SNDR and SFDR performance.
2Reliability
If DAC timing error measurement and calibration is performed, then SNDR and SFDR performance is improved, but device complexity and measurement time increase
Solution Approach 1:
The patent applies self-service by using the ADC's own internal DAC and VCO ADC resources to perform the timing error measurement and calibration. The system uses its existing components (DAC cells, VCO ADC, mixer) to measure and characterize their own timing errors without requiring external test equipment, thus reducing overall system complexity while maintaining calibration capability.
Solution Approach 2:
The patent implements universality by designing the calibration system to use the same VCO ADC and mixer resources for both normal ADC conversion operations and DAC timing error measurement. The calibration function is integrated into the existing ADC architecture, allowing these components to serve multiple purposes: signal conversion during normal operation and error measurement during calibration phases.
3Measurement precision
If multiple measurements using quadrature phase signals are performed, then timing error measurement precision is improved, but measurement time increases
Solution Approach 1:
The patent applies periodic action by performing the multi-measurement calibration process periodically rather than continuously. The calibration is executed at predetermined intervals or under specific conditions (e.g., at power-up or when performance degradation is detected), allowing the system to maintain measurement precision through multiple quadrature phase measurements while minimizing the time lost to calibration activities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method efficiently measures and corrects timing errors in DAC cells, improving the SNDR and SFDR performance of ADCs by reducing harmonic distortions and dynamic errors, especially in high-speed applications.
Implementation Method 1
A first measurement is made using a first quadrature phase signal and a second measurement is made using a second quadrature phase signal. A difference between the first measurement and the second measurement yields the timing error of the DAC cell.
Data Source
AI summary
A DAC has a plurality DAC cells, and timing mismatch among the DAC cells can introduce errors in an output of a DAC. An efficient technique can be implemented to extract the timing error of a DAC cell. The technique involves a mixer to mix the timing error to DC (DC stands for direct current, where signal frequency is zero) and a VCO ADC to observe the output of the DAC cell to measure and extract the timing error. A first measurement is made using a first quadrature phase signal and a second measurement is made using a second quadrature phase signal. A difference between the first measurement and the second measurement yields the timing error of the DAC cell. Advantageously, the mixer can be integrated within a voltage-to-current converter of the VCO ADC. The timing error can be corrected in the digital domain or analog domain.