DAC Self-Calibration for Reference Voltage Drop Linearity
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Solution Overview
Problem
High-resolution Digital to Analog Converters (DACs) face challenges in achieving accurate linearity due to code-dependent voltage drops across routing resistances, which affect the Integral Non-Linearity (INL) and are difficult to calibrate, especially in sub-binary DAC structures.
Innovation Solution
A self-calibration method for DACs that measures and adjusts each weightage independently, using a segmented sub-binary DAC architecture with split voltage reference lines and thermometric bits to minimize the impact of code-dependent voltage drops, and an auto-calibration controller to store and apply correction coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sub-binary DAC structure is used to generate finer-resolution levels, then resolution is improved, but linearity deteriorates due to inaccuracies in analog measurements of bit weightages
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements of bit weightages before final DAC operation. The system pre-determines the actual weightage of each bit through measurement and stores correction coefficients that are applied during normal operation, thereby compensating for manufacturing variations in resistor values and improving linearity while maintaining high resolution
Solution Approach 2:
The patent changes the parameter representation by transitioning from direct analog weightage measurements to digital correction coefficients. Instead of relying solely on precise analog resistor matching, the system measures weightages and converts them into digital calibration data that adjusts the DAC output, thereby decoupling resolution from manufacturing precision constraints
2Manufacturing precision
If highly accurate analog trimming procedures are used to achieve high accuracy DAC, then linearity is improved, but device complexity and cost increase
Solution Approach 1:
The patent replaces mechanical/analog trimming procedures with a digital calibration approach. Instead of physically adjusting analog components during manufacturing, the system uses digital measurements and correction coefficients stored in memory to achieve high linearity, thereby reducing device complexity and eliminating costly analog trimming processes
Solution Approach 2:
The patent implements self-service by enabling the DAC to automatically calibrate itself through internal measurements of bit weightages. The system uses its own output and an internal or external ADC to measure weightages, compute correction coefficients, and apply them without requiring external calibration equipment or manual intervention, thereby simplifying the manufacturing process
3Device complexity
If code-dependent voltage drops across routing resistances are present, then device simplicity is maintained, but measurement precision deteriorates due to impact on Integral Non-Linearity
Solution Approach 1:
The patent applies feedback by measuring the actual bit weightages (which include the effects of voltage drops across routing resistances) and using these measurements to compute correction coefficients. The system feeds back the measured weightage information into the calibration process, thereby compensating for the voltage drop effects and improving INL without requiring complex routing resistance structures
Data Source
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AI summary
A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.