DAC Reference Voltage Grouping to Reduce DNL and Chip Area
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Solution Overview
Problem
Existing digital analog conversion circuits for liquid crystal display devices face challenges in reducing the number of switch elements and reference voltages, leading to increased area and cost, while also suffering from deteriorated differential non-linearity (DNL) due to combinations of selected voltage levels.
Innovation Solution
A digital to analog conversion circuit with a decoder and interpolation circuit that classifies reference voltages into groups and uses sub-decoders to select voltages, reducing the number of switch elements and reference voltages, and optimizing voltage combinations to prevent DNL deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of reference voltages and switch elements is reduced, then the chip area and cost are reduced, but the differential non-linearity (DNL) deteriorates
Solution Approach 1:
The reference voltages are divided into multiple groups (first group, second group, third group, etc.) with different voltage levels. Sub-decoders selectively switch between these grouped reference voltages based on digital input data, enabling precise voltage selection with fewer total reference voltages while maintaining DNL performance through structured voltage distribution.
Solution Approach 2:
The patent introduces a multi-dimensional voltage selection mechanism by organizing reference voltages into groups across different voltage level dimensions. The interpolation circuit generates intermediate voltage levels by combining selected reference voltages from different groups, effectively adding a dimensional layer to the voltage output space without proportionally increasing the number of physical reference voltage lines.
2Measurement precision
If complex decoder configurations are used, then the conversion accuracy is improved, but the device complexity increases
Solution Approach 1:
The decoder function is segmented into multiple sub-decoders, each responsible for selecting reference voltages from specific groups. This segmentation distributes the decoding complexity across multiple simpler units rather than requiring one complex decoder, reducing overall device complexity while maintaining conversion accuracy through coordinated operation of sub-decoders.
Solution Approach 2:
The interpolation circuit acts as an intermediary between the sub-decoders and the final voltage output. It receives selected reference voltages from sub-decoders and generates the final interpolated voltage level, simplifying the overall decoder configuration by introducing a dedicated intermediate stage that handles the complex voltage combination logic separately from the reference voltage selection logic.
3Ease of manufacture
If the number of switch elements is reduced, then the manufacturing cost is reduced, but the voltage selection capability is limited
Solution Approach 1:
Reference voltages are segmented into multiple groups that can be selectively activated. The sub-decoders use a limited number of switch elements to select from these pre-organized groups, reducing the total switch count compared to selecting from all reference voltages individually, while maintaining comprehensive voltage selection capability through the grouped structure.
Solution Approach 2:
The voltage selection capability is enhanced by adding a group dimension to the selection mechanism. Instead of selecting reference voltages along a single linear dimension, the system selects from grouped reference voltages across multiple dimensions (group index and position within group), effectively increasing voltage selection capability without proportionally increasing switch elements.
Data Source
AI summary
Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal. An interpolation circuit receives the first and second voltages, selected by the decoder, to output a voltage level obtained on interpolation with an interpolation ratio of 1:1 (FIG. 1).