DAC Weight Calibration Using DC Offset Mismatch Detection
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) face challenges in calibrating analog weight mismatches without disrupting normal operation or requiring additional hardware, as traditional calibration methods either interrupt functionality or need extra hardware for offline calibration.
Innovation Solution
A method and apparatus for DAC weight calibration that detects mismatch between analog weights by generating specific bit sums to create a DC offset at the output, allowing for calibration without interrupting normal operation or swapping parts, using a digital control circuit to encode digital input words into control words with bits valued at -1 or 1, and adjusting weights based on detected DC levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional calibration methods are used to detect and correct weight mismatches, then manufacturing precision is improved, but device complexity increases due to extra hardware requirements
Solution Approach 1:
The digital control circuit is designed to perform dual functions: normal data encoding and calibration mode operation. By generating control words with specific bit patterns (first sum above zero, second sum below zero) during calibration, the existing circuitry detects DC offsets without requiring separate dedicated calibration hardware, thus reducing device complexity while maintaining calibration capability
Solution Approach 2:
The DAC uses its own internal resources (digital control circuit, existing analog weights, and output) to perform self-calibration. The system detects DC offsets at its own output and adjusts its own analog weights without external intervention or additional measurement equipment, eliminating the need for extra hardware while achieving weight calibration
2Manufacturing precision
If traditional calibration methods are used to detect and correct weight mismatches, then manufacturing precision is improved, but productivity decreases due to operational disruption
Solution Approach 1:
The calibration process is made dynamic and adaptive by implementing it in the time domain through controlled bit generation. The digital control circuit dynamically adjusts bit patterns to create specific sum conditions (first sum above zero, second sum below zero) that reveal DC offsets, allowing calibration to be performed adaptively without fixed operational interruptions
Solution Approach 2:
The system performs preliminary detection of DC offsets by generating specific control word patterns before final weight adjustment. This preliminary action identifies which weights need calibration, allowing the system to prepare and execute corrections efficiently without prolonged disruption to normal DAC functionality
3Reliability
If DEM is used to mitigate weight mismatch effects, then reliability is improved, but manufacturing precision deteriorates due to error spreading
Solution Approach 1:
The invention converts the harmful effect of weight mismatches into a useful calibration signal. By generating control words with specific bit sum properties, the mismatch errors manifest as detectable DC offsets at the output. This transforms the previously harmful mismatch into a beneficial measurement signal that guides weight adjustment, improving both reliability and precision
Data Source
AI summary
A method of weight calibration in a DAC (25) is disclosed. The DAC (25) comprises an input port (100) for receiving a sequence of digital input words (x[n]), each representing a digital input sample, and a digital control circuit (110) configured to encode each digital input word (x[n]) into a control word (z[n]) representing the same digital input sample. Each bit (Zi) in the control word (z[n]) has a corresponding bit weight (wi) and is in the following considered to adopt values in {−1, 1}. Furthermore, the DAC (25) comprises a set (120) of analog weights, each associated with a unique one of the bits (Zi) in the control word (z[n]), and summation circuitry (130) configured to generate an analog sample corresponding to the digital input sample by summing the bits in the control word (Zi) weighted by the respective associated analog weights. The DAC (25) also has an output (140) for outputting the analog sample. The method comprises, during a measurement procedure, for a first set of at least one bit of the control word (z[n]), generating (300) the bits of the first set, such that a first sum of the bits in the first set weighted by their respective bit weights is, on average, above zero. Furthermore, the method comprises, during the measurement procedure, for a second set of at least one bit of the control word (z[n]), generating (310) the bits of the second set, such that a second sum of the bits in the second set weighted by their respective bit weights is, on average, below zero and such that the sum of the first sum and the second sum is, on average, equal to zero. The method also comprises detecting (330) a DC level at the output of the DAC during the measurement procedure. The method further comprises adjusting (340) at least one analog weight in response to the detected DC level. A corresponding DAC, a corresponding electronic apparatus, and a corresponding integrated circuit are also disclosed.