DAC Circuit Without Sample-Hold for Fast Linear Output
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Solution Overview
Problem
Conventional digital/analog converter circuits face challenges in reducing settling error and circuit scale while achieving high definition and gradation, due to increased time constants and power consumption, which affect the response speed and linearity of output voltage.
Innovation Solution
The digital/analog converter circuit design eliminates the sample/hold circuit between the selection and amplifier sections, reducing the time constant and circuit scale, and allocates different digital values to each step voltage, with adjustable settling times and voltage values to ensure monotonous increase and linearity of the output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a sample/hold circuit with a sufficiently large capacitance value is used to suppress switch field through noise, then noise suppression is improved, but the time constant increases and response speed deteriorates
Solution Approach 1:
The invention extracts and removes the sample/hold circuit from the signal path between the reference voltage generation circuit and the output buffer. By eliminating this circuit component, the patent avoids the inherent contradiction between using large capacitance for noise suppression and the resulting increase in time constant that degrades response speed.
2Speed
If the resistance value of the sample/hold circuit is reduced to decrease the time constant, then response speed is improved, but the switch size must increase which increases switch field through noise
Solution Approach 1:
The invention extracts and removes the sample/hold circuit from the signal path, thereby eliminating the need to compromise between reducing resistance for faster response and increasing switch size that would worsen noise. The removal of this circuit component resolves the contradiction at its source.
3Speed
If the resistance value of the resistance divider circuit is reduced to decrease the time constant, then response speed is improved, but power consumption increases
Solution Approach 1:
The invention removes the sample/hold circuit from the signal path, eliminating the need to reduce the resistance divider circuit's resistance value for speed improvement. This avoidance allows the resistance divider to maintain higher resistance values, thereby reducing power consumption while still achieving fast response through the eliminated sample/hold circuitry.
4Measurement precision
If enhancement of bit precision is implemented, then conversion precision is improved, but the circuit scale of the selector increases exponentially
Solution Approach 1:
The invention removes the sample/hold circuit and its associated selector from the signal path. This elimination avoids the exponential increase in selector circuit scale that would otherwise be required to achieve high bit precision, while maintaining conversion precision through the direct connection architecture.
Data Source
AI summary
A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).