Tri-Level DAC Cell 0-State Switching to Suppress Mismatch and THD
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Solution Overview
Problem
Conventional tri-level digital-to-analog converters (DACs) suffer from non-linear distortion due to static mismatch between PMOS and NMOS reference circuits when no common-mode feedback is used, and total harmonic distortion (THD) degradation due to drain voltage modulation when common-mode feedback is used.
Innovation Solution
A tri-level DAC element with a single DAC cell comprising two reference circuits and a switch circuit, where the switch circuit controls the interconnection between the reference circuits and the output port based on a control input, allowing at least one reference circuit to be coupled to the output during the '0' state, effectively suppressing mismatch by intentionally outputting mismatch in the '0' state and using a doubled sampling frequency to divide the '0' state into two phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If no common-mode feedback circuit is connected to the transimpedance amplifier, then the tri-level DAC element structure is simpler, but non-linear distortion occurs due to static mismatch between reference circuits
Solution Approach 1:
The invention divides the '0' state period into two phases and segments the mismatch suppression function across multiple states. By coupling reference circuits to the output during the '0' state and using the difference between phases to cancel mismatch, the patent achieves linearity improvement without requiring a complex common-mode feedback circuit throughout all states.
Solution Approach 2:
The invention employs periodic action by dividing the '0' state into two phases and alternating the coupling of reference circuits to the output. This periodic switching creates a time-averaged cancellation effect that suppresses static mismatch between PMOS and NMOS reference circuits while maintaining simplicity.
2Manufacturing precision
If a common-mode feedback circuit is connected to the transimpedance amplifier, then non-linear distortion is mitigated, but total harmonic distortion degrades due to drain voltage modulation
Solution Approach 1:
The invention performs preliminary mismatch suppression by coupling reference circuits to the output during the '0' state before the actual signal conversion states. This preliminary action establishes a reference level that cancels static mismatch, eliminating the need for continuous common-mode feedback and thereby preventing drain voltage modulation that causes THD.
Solution Approach 2:
The invention converts the potentially harmful static mismatch between reference circuits into a beneficial cancellation mechanism. By intentionally coupling mismatched reference circuits to the output during the '0' state and exploiting the difference between two phases, the mismatch signal is used to suppress itself, achieving linearity without the harmful side effects of CMFB.
3Manufacturing precision
If reference circuits are coupled to the output during the '0' state, then mismatch is suppressed, but device complexity increases due to additional switching control
Solution Approach 1:
The switch circuit in the invention serves multiple functions: it controls the three operational states (+1, 0, -1) of the DAC element and simultaneously implements mismatch suppression by coupling reference circuits to the output during the '0' state. This multi-functionality reduces the need for separate control mechanisms, thereby limiting the increase in device complexity.
Data Source
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AI summary
A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a "0" state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.