Distributed Arithmetic Feed Forward Equalizer With Offset-Binary LUTs
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Solution Overview
Problem
Current distributed arithmetic feed forward equalizer (FFE) architectures in data link receivers face challenges in device size scaling, power optimization, and faster operating speeds, particularly in reducing power consumption while maintaining effective signal equalization for PAM-4 signals prone to noise degradation.
Innovation Solution
A power-optimized distributed arithmetic (DA) architecture for feed forward equalizers that utilizes look-up tables in offset binary format, reducing the size of DA LUTs by half and incorporating adjustment LUTs to compensate for the reduction in signal magnitude, thereby minimizing downstream adder logic complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional distributed arithmetic FFE architecture is used, then signal equalization is achieved, but power consumption and device size are excessive
Solution Approach 1:
The patent divides the equalization process into two independent stages: a distributed arithmetic FFE stage that handles the majority of equalization function, and a CTLE stage that provides residual equalization. This segmentation allows the power-hungry DA FFE to operate with reduced precision requirements while the CTLE cleans up remaining signal degradation, achieving overall equalization with lower total power consumption.
Solution Approach 2:
The patent changes the precision parameter of the DA FFE from high precision to reduced precision (fewer bits), and compensates by adjusting the CTLE parameters (gain, pole-zero locations) to optimize residual equalization. This parameter transformation maintains equalization quality while reducing the power consumption of the DA FFE component.
2Area of stationary object
If device size is reduced for scaling, then power consumption decreases, but operating speed may be compromised
Solution Approach 1:
By segmenting the equalization function between DA FFE and CTLE, the patent reduces the computational burden on the DA FFE, allowing it to be implemented with smaller, faster logic elements. The CTLE handles the continuous-time residual equalization in parallel, avoiding the need for large sequential adder trees that would slow down operation.
Solution Approach 2:
The patent replaces the traditional mechanical/combinatorial approach of full-precision DA FFE with a hybrid approach where reduced-precision DA FFE outputs are processed by an analog CTLE. This substitution allows smaller device size while maintaining high operating speeds because the CTLE operates in the continuous domain without discrete timing constraints.
3Device complexity
If downstream adder logic is simplified to reduce power, then device complexity decreases, but signal processing accuracy may be affected
Solution Approach 1:
The patent segments the precision requirements between the DA FFE and CTLE stages. The DA FFE uses simplified adder logic with reduced precision, while the CTLE provides the necessary precision enhancement for residual equalization. This segmentation allows complex precision requirements to be distributed rather than concentrated in one high-complexity adder tree.
Solution Approach 2:
The CTLE acts as an intermediary between the reduced-precision DA FFE output and the final equalized signal. It compensates for the precision loss from simplified adder logic by providing analog gain adjustment and frequency-dependent equalization, thereby maintaining overall signal processing accuracy without requiring complex digital adder logic.
Data Source
AI summary
A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.