Debug Access Filter Router Arbiter Logic for Multi-System Debugging

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Solution Overview

Problem

Legacy debugging systems lack a standard mechanism for secure, multi-access, collaborative debugging of platforms and components, particularly failing to enable multiple debug and test systems (DTSs) to debug the same target system simultaneously, which limits usability and collaboration across different vendors and components.

Innovation Solution

The implementation of Debug Access Filter, Router, and Arbiter (DAFRA) logic and Multi-Access Handler (MAH) logic, which provide secure debug access, filter, and arbitrate commands or messages from different DTSs, enabling multiple DTSs to collaborate on debugging the same target system through secure sessions and message exchanges at the debug protocol level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple debug and test systems are used to debug different platform components separately, then debugging coverage is improved, but device complexity and lack of collaboration capability worsen

Engineering Contradiction:
Improvedebugging coverageVSAvoidsystem integration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple independent debug and test systems into a unified collaborative debugging framework. The platform logic intercepts and coordinates debug commands from multiple DTSs, enabling them to work together on the same target system simultaneously. This combining approach allows comprehensive debugging coverage while managing system complexity through centralized coordination.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal debugging interface that allows different debug and test systems from various vendors to access and debug the same platform components. The platform logic acts as a universal mediator that standardizes access mechanisms, enabling multi-vendor DTSs to collaborate through a common protocol and interface layer.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If a single debug system is used to debug multiple components sequentially, then device complexity is reduced, but productivity and debug time worsen

Engineering Contradiction:
Improvesystem configuration simplicityVSAvoiddebugging efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements periodic action by enabling multiple debug systems to operate in parallel on different components simultaneously. Instead of sequential single-system debugging, multiple DTSs can periodically access and debug different platform components at the same time, significantly improving productivity while maintaining manageable system complexity through the platform logic coordinator.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If multiple physical debuggers are deployed simultaneously, then debugging capability is improved, but cost and supply chain burden worsen

Engineering Contradiction:
Improvesimultaneous debug capabilityVSAvoidnumber of physical debuggers
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent introduces platform logic as an intermediary layer between multiple physical debuggers and the target platform components. This mediator coordinates access from multiple DTSs, allowing them to collaborate on debugging the same target system without requiring each debugger to independently access hardware resources. The intermediary manages resource sharing and coordination, reducing the need for additional physical debuggers while maintaining simultaneous debugging capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20230315596A1Platform and platform component debug by multiple debugging systems
Publication Date: 2023.10.05 INTEL CORP
  • US20230315596A1 patent drawing
  • US20230315596A1 patent drawing
  • US20230315596A1 patent drawing

AI summary

Embodiments herein relate to a logic configured to: identify, based on a header of a first packet, that the first packet is related to a first debug process of a component to which the logic is communicatively coupled, wherein the first debug process is performed by a first DTS; identify, based on a header of a second packet, that the second packet is related to a second debug process of the component, wherein the second debug process is performed by a second DTS; route, based on the identification that the first packet is related to the first debug process, the first packet between the component and the DTS; and route, based on the identification that the second packet is related to the second debug process, the second packet between the component and the DTS. Other embodiments may be described and/or claimed.