Network Clock Synchronization Using Directed Acyclic Graph Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The Best Master Clock Algorithm (BMCA) for Precision Time Protocol (PTP) fails to account for clock performance in data networks and is susceptible to path failures due to link breakages in spanning trees, particularly in Low-power and Lossy Networks (LLN) with constrained resources and high loss rates.
Innovation Solution
Incorporating timing information into routing advertisement messages and using a time-optimized objective function to establish an optimized loopless time topology within directed acyclic graphs (DAGs), allowing network devices to select the best parent device and generate a synchronized network clock, enabling rerouting and path recovery, and supporting multiple DAGs for concurrent synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the Best Master Clock Algorithm (BMCA) is used for clock synchronization in PTP, then the spanning tree structure provides a simple synchronization mechanism, but the system becomes susceptible to path failures due to link breakages in the spanning tree
Solution Approach 1:
The patent segments the single spanning tree into multiple directed acyclic graphs (DAGs), allowing network devices to belong to multiple time topologies simultaneously. This segmentation enables alternative paths for clock synchronization, reducing susceptibility to path failures while maintaining operational simplicity through automated DAG selection based on timing information.
Solution Approach 2:
The patent introduces dynamic adaptation where network devices can switch between different DAGs based on real-time timing information and link status. The system dynamically adjusts the time topology by selecting optimal parent devices and DAGs, transforming the static spanning tree into a resilient dynamic structure that recovers from link breakages.
2Device complexity
If traditional routing advertisement messages are used without timing information, then the message format remains simple, but clock performance and timing quality cannot be optimized
Solution Approach 1:
The patent merges timing information with existing routing advertisement messages (such as RPL DIO messages), combining clock performance metrics, timing quality parameters, and routing data into a single integrated message structure. This merging enables clock optimization without requiring separate complex message protocols, maintaining message format simplicity while achieving precise timing measurement.
Solution Approach 2:
The patent makes the routing advertisement message universal by enabling it to carry both traditional routing information and timing information simultaneously. The same message structure serves dual purposes: route discovery and clock performance evaluation, eliminating the need for separate timing messages and simplifying the overall system architecture.
3Device complexity
If a single DAG structure is used for clock synchronization, then the topology is simple and easy to manage, but the system cannot provide robust path recovery in case of link failures
Solution Approach 1:
The patent segments the synchronization topology into multiple DAGs that can operate independently. Each DAG represents an alternative time topology, and network devices can switch between DAGs based on link status. This segmentation provides inherent path recovery capability while maintaining the simplicity of individual DAG structures through standardized formation and management protocols.
Solution Approach 2:
The patent implements preliminary action by pre-establishing multiple DAGs and alternative parent relationships during network initialization and operation. When link failures occur, devices already have pre-configured alternative paths and can quickly switch between DAGs without requiring complex real-time topology reconstruction, thus providing robust path recovery.
4Productivity
If network devices attach to a single parent device, then the attachment process is simple and fast, but the system lacks redundancy and cannot maintain synchronization during link failures
Solution Approach 1:
The patent introduces dynamic attachment where network devices can simultaneously attach to multiple parent devices across different DAGs, with the ability to dynamically select the optimal parent based on real-time timing information and link quality. This dynamic multi-parent attachment maintains high attachment speed while providing redundancy for synchronization maintenance during link failures.
Solution Approach 2:
The patent applies parameter changes by monitoring timing information and link status parameters to dynamically adjust parent selection. Devices change their attachment parameters based on measured clock performance and link quality metrics, allowing them to switch between parents to maintain synchronization reliability without sacrificing attachment efficiency.
Data Source
AI summary
In one embodiment, a method comprises receiving, by a network device, one or more advertisement messages comprising timing information describing a quality of a network clock that is originated by a master clock device at a root of a directed acyclic graph (DAG); the network device executing an objective function for the DAG providing an optimized loopless time topology for the network clock, synchronized to the master clock device, based on the timing information; and the network device attaching to a parent device in the DAG based on the objective function, for optimized generation of the network clock by the network device.