Extended Regular Expression Matching in Directed Acyclic Graphs via Assertion Simulation
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Solution Overview
Problem
Conventional approaches for extended regular expression (ERE) matching in directed acyclic graphs (DAGs) are complex and error-prone, particularly when handling EREs, and often only work for conventional regular expressions, failing to effectively verify and test systems during IC design verification and testing.
Innovation Solution
The solution reduces ERE matching in DAGs to regular expression matching using SystemVerilog Assertions (SVA) checking in circuit simulation, delegating semantic and syntactic checking complexity to the circuit simulator, and employs DAG size reduction for improved performance, allowing ERE matching on multiple DAGs in a single simulation run.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional approaches are used for ERE matching in DAGs, then the matching can be performed, but the complexity of the approach increases and errors become more frequent
Solution Approach 1:
The patent introduces an intermediary conversion process that transforms the complex ERE matching problem into a standard regular expression matching problem. By using a converter component that translates ERE patterns into equivalent regular expressions, the system leverages成熟 simulation technologies to achieve reliable matching without directly implementing complex ERE matching logic, thereby reducing errors and improving reliability.
Solution Approach 2:
The patent replaces the mechanical/algorithmic approach of direct ERE matching with a simulation-based approach. Instead of implementing complex matching algorithms that are error-prone, the system uses circuit simulation with converted regular expressions, leveraging the robustness of simulation technologies to achieve more reliable and maintainable matching functionality.
2Reliability
If ERE matching is implemented directly in DAGs, then comprehensive verification is achieved, but the performance and execution time deteriorate
Solution Approach 1:
The patent extracts the complex ERE processing logic from the performance-critical matching path. By separating the conversion process from the simulation process, the system performs the complex ERE-to-regex conversion once before simulation, rather than during simulation execution. This extraction of complex processing from the time-critical path maintains verification completeness while significantly improving matching performance.
3Ease of manufacture
If conventional regular expression matching is used, then the implementation is simpler, but it fails to handle extended regular expressions and reduces verification effectiveness
Solution Approach 1:
The patent creates a universal solution that handles both conventional regular expressions and extended regular expressions through a unified conversion approach. The converter component can process various ERE patterns and transform them into standard regular expressions, allowing the system to maintain implementation simplicity while gaining the versatility to handle complex ERE patterns that are essential for comprehensive IC design verification.
Data Source
AI summary
A directed acyclic graph (DAG) and an extended regular expression (ERE) may be received. A circuit design may be generated based on the DAG. A cover property may be generated based on the ERE. The circuit design may be simulated. A first result may be determined based on whether the cover property is satisfied during the simulating the circuit design. It may be determined whether the ERE matches a path in the DAG based on the first result.