Memory Caching for DAG Subgraph Data Transfer Lag

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Solution Overview

Problem

In distributed computing using Directed Acyclic Graphs (DAGs), the transfer of large amounts of data via data pipelines at each iterative step of an iterative algorithm is inefficient, leading to significant data transfer lag and bandwidth utilization.

Innovation Solution

Implementing a memory caching service within a DAG distributed execution engine to store and access previously processed subgraphs locally, eliminating the need for repeated data transfers between iterations by caching subgraphs for subsequent processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred via data pipelines at each iterative step, then data can be accessed by processing devices, but data transfer lag and bandwidth utilization increase significantly

Engineering Contradiction:
Improvedata access speedVSAvoiddata transfer lag
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-fetching and caching subgraph data in the memory cache of processing devices before it is needed for processing. The data caching service predicts which subgraphs will be needed and loads them into local memory in advance, eliminating the need for time-consuming data transfers during actual processing iterations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a memory cache as an intermediary layer between the distributed storage system and processing devices. This cache serves as a buffer that holds frequently accessed subgraph data locally, mediating between the slow distributed storage and the fast processing units, thereby reducing data transfer lag without compromising data accessibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If data is transferred via data pipelines at each iterative step, then processing devices can access updated data, but bandwidth utilization increases due to repeated transfers

Engineering Contradiction:
Improveprocessing throughputVSAvoiddata transfer volume
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by allowing each processing device to maintain its own local copy of subgraph data in its memory cache. Instead of requiring all devices to access data from a central distributed storage system, each device has local access to the data it needs, reducing redundant data transfers across the network while maintaining processing productivity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses copying by creating local replicas of subgraph data in the memory caches of processing devices. Rather than transferring the same data repeatedly over the network, the system makes copies of the data and stores them locally at each processing device, eliminating redundant data transfers while maintaining data availability for parallel processing.

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If subgraphs are stored in distributed storage system, then data can be accessed by multiple devices, but repeated access requires repeated data transfers

Engineering Contradiction:
Improvedata accessibilityVSAvoiddata transfer time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The data caching service performs preliminary action by predicting which subgraphs will be needed by which processing devices and pre-loading them into the respective memory caches before the processing iterations begin. This eliminates the need for repeated data transfers during execution while maintaining data accessibility for multiple devices.

Inventive Principle:
Principle #10Preliminary action

4Loss of time

If memory cache is implemented, then data transfer requirements are reduced, but additional memory resources are required

Engineering Contradiction:
Improvedata transfer lagVSAvoidmemory cache size
Core Design Contradiction:
Loss of timeVSVolume of stationary object

Solution Approach 1:

The patent applies partial action by implementing memory caches only at processing devices that need them, rather than requiring all devices to have full caching capabilities. The system selectively caches data based on predicted access patterns and processing needs, reducing the total memory overhead while still achieving the benefit of reduced data transfer lag for the critical processing paths.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8229968B2Data caching for distributed execution computing
Publication Date: 2012.07.24 MICROSOFT TECHNOLOGY LICENSING LLC
  • US8229968B2 patent drawing
  • US8229968B2 patent drawing
  • US8229968B2 patent drawing

AI summary

Embodiments for caching and accessing Directed Acyclic Graph (DAG) data to and from a computing device of a DAG distributed execution engine during the processing of an iterative algorithm. In accordance with one embodiment, a method includes processing a first subgraph of the plurality of subgraphs from the distributed storage system in the computing device. The first subgraph being processed with associated input values in the computing device to generate first output values in an iteration. The method further includes storing a second subgraph in a cache of the device. The second subgraph being a duplicate of the first subgraph. Moreover, the method also includes processing the second subgraph with the first output values to generate second output values if the device is to process the first subgraph in each of one or more subsequent iterations.