Sub-graph Identification for DAG Processing Memory Constraints
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Solution Overview
Problem
Existing data processing techniques, such as neural network and graphics processing, face inefficiencies in handling large amounts of data due to inadequate management of operations and memory constraints, leading to suboptimal execution and increased memory traffic.
Innovation Solution
A system comprising a host processor and an offload processor, where the host processor identifies and selects sub-graphs of operations from a directed acyclic graph (DAG) that map to corresponding execution units and storage elements, optimizing buffer sizes through simulation to minimize memory constraints and reduce external memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data processing techniques process and generate considerable amounts of data using operations, then processing capability is improved, but memory constraints and memory traffic increase
Solution Approach 1:
The patent segments the directed acyclic graph of operations into multiple sub-graphs that can be independently mapped to processing modules. This segmentation allows operations to be distributed across multiple execution units, improving processing capability while managing memory traffic by localizing data access within each sub-graph's mapping context.
Solution Approach 2:
The patent introduces a mapping dimension that connects operations to execution units and connections to storage elements. This dimensional transformation enables the system to process considerable amounts of data by utilizing the multi-dimensional mapping space, thereby improving processing capability without proportionally increasing memory traffic.
2Productivity
If buffer sizes are increased to handle data processing operations, then processing efficiency is improved, but memory constraints are worsened
Solution Approach 1:
The patent performs preliminary simulation of sub-graph execution to estimate required buffer sizes before actual data processing. This preliminary action allows the system to allocate memory efficiently, ensuring processing efficiency is maintained while avoiding excessive buffer allocation that would worsen memory constraints.
Solution Approach 2:
The patent dynamically adjusts buffer size parameters based on simulation results and actual processing requirements. By changing buffer size parameters adaptively rather than using fixed large allocations, the system maintains processing efficiency while respecting memory constraints.
3Speed
If sub-graph mapping to execution units is optimized, then processing speed is improved, but system complexity increases
Solution Approach 1:
The patent implements self-service mechanisms where the system automatically performs sub-graph identification, simulation, and mapping optimization without requiring external intervention. This automation improves processing speed through optimized mapping while managing system complexity by encapsulating the complexity within automatic routines rather than requiring manual management.
Data Source
AI summary
The present disclosure relates to a system, method and non-transitory computer-readable storage medium for handling data. From a directed acyclic graph, DAG, of operations on input data a sub-graph of operations is identified and issued as task data to be executed by a processing module, wherein each of the operations in the sub-graph maps to a corresponding execution unit of the processing module of the system and wherein each connection between operations maps to a corresponding storage element of the processing module. The sub-graph is identified such that a simulation of an execution of the operations of the candidate sub-graph according to a determined size of the processing unit of said input data shows that the processing module can execute the operations of the sub-graph such that memory constrains of the processing module are met and read-write operations to memory external to the processing module are avoided or reduced.