DAG Template for Cross-Hardware Data Pipeline Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Developers face difficulties in writing code for specialized processing devices due to the lack of standardized application programming interfaces (APIs) across different manufacturers, making it time-consuming and requiring significant modifications when switching hardware.
Innovation Solution
A computing system that uses a directed acyclic graph (DAG) template to select and route processing stages across multiple communicatively linked processing devices, such as CPUs, GPUs, and FPGAs, ensuring efficient data pipeline execution without needing to customize code for specific devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If developers write code for specialized processing devices using manufacturer-specific APIs, then the code can execute on those devices, but it requires significant modifications when switching hardware and is time-consuming to develop
Solution Approach 1:
The patent introduces a standardized API layer as an intermediary between the developer's code and manufacturer-specific processing devices. This intermediary translates generic processing requests into device-specific operations, allowing code to run across different hardware without modification while maintaining full functionality on specialized devices.
Solution Approach 2:
The patent creates a universal processing framework that can interface with multiple types of specialized processing devices through a single standardized API. This universal layer enables the same code to execute on CPUs, GPUs, FPGAs, and other specialized devices without requiring hardware-specific implementations.
2Productivity
If developers create hardware-specific code for specialized processing devices, then optimization for that specific device is achieved, but code requires significant modifications when switching hardware
Solution Approach 1:
The standardized API acts as a mediator that preserves computational efficiency by translating optimized processing requests into device-specific operations. Each specialized device can execute highly optimized routines while the intermediary ensures these optimizations remain accessible through a hardware-agnostic interface.
Solution Approach 2:
The patent segments the processing system into two independent layers: a hardware-agnostic standardized API layer and hardware-specific optimized execution layers. This segmentation allows each layer to be optimized independently while maintaining their coordination, enabling both portability and performance.
3Adaptability or versatility
If standardized APIs are implemented across different processing devices, then code portability is improved, but device complexity increases due to the need for translation layers
Solution Approach 1:
The standardized API serves as a thin intermediary layer that manages complexity by providing a uniform interface while handling device-specific complexities internally. This approach isolates complexity within the translation layer without exposing it to developers, maintaining simple code while supporting complex hardware.
Data Source
AI summary
A computing system is provided, including a processor configured to receive a directed acyclic graph (DAG) template specifying a data pipeline of a plurality of processing stages. For each processing stage, the processor may be further configured to select a respective processing device of a plurality of communicatively linked processing devices. The processor may be further configured to determine a routing sequence between the plurality of processing devices according to the DAG template. The processor may be further configured to transmit a plurality of input packets encoding the plurality of processing stages to the respective processing devices selected for the processing stages as specified by the routing sequence. In response to transmitting the plurality of input packets, the processor may be further configured to receive, from a processing device of the plurality of processing devices, one or more output packets encoding a processing result of the data pipeline.