Scheduler Circuit for DAG Vector Data Transfer
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Solution Overview
Problem
Conventional general-purpose programmable processors are inefficient in exploiting parallelism and optimizing data paths and memory bandwidth for computer vision tasks, limiting their performance and flexibility in handling evolving computer vision processing demands.
Innovation Solution
A scheduler circuit and hardware engines configured to execute directed acyclic graphs, optimizing data paths and memory bandwidth by scheduling operators based on readiness and operating on variable-size multidimensional vectors, enabling efficient execution of computer vision tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional general-purpose processors use aggressive pipelining and out-of-order execution to extract parallelism, then processing speed is improved, but data and control dependencies limit further performance gains
Solution Approach 1:
The patent segments the computation into a directed acyclic graph of operators, where each operator represents an independent computational unit. This segmentation allows the system to execute operators in parallel based on data availability, resolving the contradiction by enabling speed improvement through parallelism while maintaining reliability through explicit dependency management in the DAG structure.
Solution Approach 2:
The patent implements a dynamic scheduler that adapts the execution order of operators based on real-time data availability and readiness. This dynamic approach allows the system to optimize both speed and reliability by flexibly adjusting the execution schedule according to actual data flow conditions, rather than relying on fixed pipelining or out-of-order execution.
2Use of energy by moving object
If specialized engines are used for computer vision tasks, then power efficiency and cost are improved, but flexibility to support new or enhanced tasks deteriorates
Solution Approach 1:
The patent creates a universal coprocessor architecture using a directed acyclic graph framework that can accommodate various computer vision operators (e.g., convolution, pooling, normalization). This multi-functional design achieves power efficiency through specialized hardware execution while maintaining flexibility by allowing the same framework to support evolving computer vision tasks through software-defined operator graphs.
3Ease of manufacture
If compilers are used to extract inherent parallelism from conventional programming languages, then implementation ease is improved, but the ability to exploit detailed problem domain understandings deteriorates
Solution Approach 1:
The patent performs preliminary action by pre-compiling computer vision algorithms into a standardized directed acyclic graph representation with optimized data paths and memory access patterns. This preliminary preparation enables easy implementation through direct hardware execution while simultaneously capturing detailed problem domain understandings in the operator definitions and data flow graph structure.
Data Source
AI summary
An apparatus includes a scheduler circuit and a plurality of hardware engines. The scheduler circuit may be configured to (i) store a directed acyclic graph, (ii) parse the directed acyclic graph into a plurality of operators and (iii) schedule the operators in one or more data paths based on a readiness of the operators to be processed. The hardware engines may be (i) configured as a plurality of the data paths and (ii) configured to generate one or more output vectors by processing zero or more input vectors using the operators.