Directed Acyclic Graph Vertex Merging for Memory Reduction
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Solution Overview
Problem
Existing methods for sequential computer-implemented operations require increased memory usage and high memory bandwidth due to the need for intermediate storage of results from each filter operation in image processing and similar tasks, leading to inefficient memory allocation.
Innovation Solution
The method involves generating a directed acyclic graph (DAG) to represent operations and merging predecessor and successor vertices connected by a single edge, reducing the number of directed edges and thus the memory space required for storing output data, while ensuring that the merger does not increase computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If intermediate storage is allocated for each filter operation result, then task execution can proceed in sequence with proper data transformation, but memory usage and memory bandwidth requirements increase
Solution Approach 1:
The patent merges consecutive vertices in the DAG where the predecessor has only one outgoing edge, combining their operations into a single vertex. This eliminates intermediate storage requirements between these operations, reducing memory usage while maintaining correct data transformation through the merged operation sequence.
Solution Approach 2:
The patent discards intermediate buffer allocations for merged vertices by eliminating the need to store intermediate results when operations are combined. The computational logic is preserved within the merged vertex, recovering memory space that would otherwise be occupied by intermediate buffers.
2Productivity
If buffer memory is allocated for each intermediate result, then sequential operations can be properly executed, but the system requires high memory bandwidth
Solution Approach 1:
By merging vertices with single outgoing edges, the patent eliminates intermediate buffer writes and reads, reducing memory bandwidth requirements. The sequential execution capability is maintained through the merged vertex's internal operation sequencing, avoiding unnecessary memory access cycles.
3Quantity of substance
If the DAG structure is optimized by merging vertices, then the number of directed edges and memory space requirements decrease, but the complexity of graph processing increases
Solution Approach 1:
The patent applies segmentation by identifying specific mergeable vertex patterns (predecessor with single outgoing edge) and applying merges systematically. This structured approach to graph optimization reduces memory space while keeping the processing complexity manageable through clear merge criteria and iterative application.
Data Source
AI summary
Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.