Daisy-Chain Memory Architecture with Redundant Bypass Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern computer systems with multiple processors and large memories face challenges in memory access time and reliability due to complex bus structures, where daisy-chained memory modules experience increased access time with position and are prone to reliability issues from malfunctioning modules.
Innovation Solution
A computer system communications architecture with multiple modules arranged in daisy-chains, featuring redundant paths that allow any single module to be bypassed in case of malfunction, maintaining data connection and reducing latency or increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If daisy-chained memory modules are used to support large memories, then memory capacity increases, but access time increases with module position in the chain
Solution Approach 1:
The memory system is divided into multiple banks, each with its own controller. This segmentation allows parallel access to different memory banks, reducing the effective access time while maintaining large total capacity. The controller can independently manage multiple banks simultaneously.
Solution Approach 2:
The patent introduces a new dimension of organization by adding bank controllers that can independently manage multiple memory banks. This creates a two-dimensional access structure (bank dimension + module position dimension) that allows parallel operations, effectively reducing access time while maintaining capacity.
2Quantity of substance
If daisy-chained memory modules are used to support large memories, then memory capacity increases, but the system becomes more prone to reliability issues from malfunctioning modules
Solution Approach 1:
By dividing the memory system into independent banks with separate controllers, a malfunction in one bank does not propagate to other banks. This isolation improves reliability while maintaining the ability to support large total memory capacity through the combination of multiple banks.
Solution Approach 2:
The bank controller acts as an intermediary between the processor and multiple memory banks. It manages access to individual banks and can isolate failures, preventing a single point of failure from affecting the entire memory system while still providing access to large total capacity.
3Adaptability or versatility
If complex bus structures are used to connect multiple processors and memory, then system capability increases, but access time increases due to the complexity of the path
Solution Approach 1:
The memory system is segmented into multiple banks with independent controllers, allowing parallel access paths. This reduces the effective path complexity from the processor to memory by enabling simultaneous access to multiple banks, thereby reducing access time while maintaining system capability.
Solution Approach 2:
The bank controllers dynamically manage access to different memory banks based on the current operation requirements. This dynamic allocation allows the system to optimize access paths and reduce effective access time while maintaining the versatility to handle various memory operations.
Data Source
AI summary
A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.