Daisy Chaining Nonvolatile Memories Parallel Address Paths
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Solution Overview
Problem
Existing cloud computing data storage infrastructures face inefficiencies due to serialized address propagation, leading to increased response times and system complexity.
Innovation Solution
Implementing a parallel-connected address/command electrical path and utilizing multiplexers and electronic switches to temporarily remove addresses from the serializing chain, allowing each memory device to receive addresses independently and reducing pipelining delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serialized address propagation is used in data storage infrastructures, then device complexity is reduced, but response time increases
Solution Approach 1:
The patent segments the address propagation process by introducing separate parallel address/command electrical paths for each memory device in the daisy chain. Instead of a single serialized path, each memory device has its own dedicated address/command inputs, allowing simultaneous address delivery to multiple devices and eliminating the time penalty of sequential address propagation.
Solution Approach 2:
The patent transitions from a one-dimensional serialized address propagation model to a multi-dimensional parallel architecture. By adding parallel address/command paths alongside the existing data daisy chain, the system achieves simultaneous address delivery to multiple memory devices without increasing physical complexity, effectively adding a temporal dimension to address propagation.
2Device complexity
If serialized address chains are used, then system complexity is reduced, but data access speed decreases
Solution Approach 1:
The patent segments the address delivery mechanism by providing independent address/command electrical paths to each memory device. This segmentation allows addresses to be delivered in parallel to multiple devices simultaneously, dramatically increasing data access speed while maintaining relatively simple device-level structures.
Solution Approach 2:
The patent implements preliminary action by pre-configuring parallel address/command paths for all memory devices before data access operations. This preliminary setup enables immediate parallel address delivery without requiring sequential initialization, thereby accelerating data access speeds from the outset.
3Loss of time
If parallel address paths are implemented for each memory device, then response time is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the parallel address/command paths to serve multiple functions: address delivery, command transmission, and data enablement. These paths are universally used across all memory devices in the daisy chain, eliminating the need for separate dedicated paths for each function and reducing overall system complexity despite the parallel architecture.
Solution Approach 2:
The patent merges the address and command transmission functions into unified parallel paths that operate simultaneously for all memory devices. By combining these functions into a single infrastructure rather than separate dedicated paths, the system achieves fast response times while minimizing the complexity increase that would result from fully separate address/command pathways.
Data Source
AI summary
A host accessing memory devices by providing common address and command information on a parallel-connected serial bus to each of the memory devices and shifting data in the memory devices through a daisy-chain serial interface.