Daisy Chain Non-Volatile Memory Interface for Throughput
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Solution Overview
Problem
NAND flash memory devices experience reduced throughput due to capacitive loading and slow access times when multiple devices are connected in parallel, leading to signal degradation and accumulated access times.
Innovation Solution
Implementing a daisy chain connection of multiple flash memory controllers to avoid bus loading, using buffers and multiplexers to manage data transfer between devices, allowing sequential access of multiple memory devices to improve throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple NAND flash memory devices are connected in parallel on a common bus, then simultaneous access to multiple devices is enabled, but capacitive loading degrades signal quality and reduces maximum useful throughput
Solution Approach 1:
The patent divides the parallel bus structure into sequential serial connections. Each memory device is connected in series to the next device through a chain of controllers, segmenting the data path. This segmentation eliminates the capacitive loading problem of parallel connections while still enabling access to multiple devices by sequentially traversing the chain.
Solution Approach 2:
The patent introduces controllers as intermediary components between memory devices. These controllers manage the sequential data transfer between devices in the chain, coordinating read and write operations. The controllers act as mediators that enable simultaneous operations across multiple devices without direct parallel electrical connections, thus avoiding signal degradation.
2Object-affected harmful factors
If multiple NAND flash memory devices are accessed sequentially one at a time, then signal quality is maintained, but access times accumulate and overall throughput is reduced
Solution Approach 1:
The patent enables continuous useful action by allowing multiple memory devices to operate simultaneously in the sequential chain. While one device is being accessed, other devices in the chain can be prepared for or completing operations, eliminating idle time between sequential accesses. This continuity maintains signal quality through sequential access while preventing access time accumulation.
Solution Approach 2:
The patent implements preliminary action by pre-positioning data in buffers at intermediate controllers. Data can be loaded into buffers at one device while the read operation at another device is already in progress, preparing the data path in advance. This eliminates waiting time and maintains continuous throughput without compromising signal integrity.
3Ease of operation
If all input/output pins are placed in parallel for multiple memory devices, then direct access to all devices is enabled, but capacitive loading increases and degrades bus signal quality
Solution Approach 1:
The patent transitions from a spatial parallel arrangement (all pins on the same bus) to a temporal sequential arrangement (devices accessed one after another in a chain). This dimensional change from space to time eliminates the capacitive loading issue while maintaining ease of operation through the sequential chain architecture, where each device can still be accessed directly in turn.
Data Source
AI summary
Various embodiments of the invention connect multiple non-volatile memory controllers in a daisy chain manner, so the multiple memory devices may be accessed from a common host controller. Data and control signals may be daisy-chained in this way, so that many memory devices may be connected together, while not increasing the loading on individual signals lines. Transfer with the various memory devices may be interleaved, so that the relatively slow times of the memory devices doesn't slow down the overall throughout of the memory stem.