Multi-Chip Daisy-Chain Output Aggregation Without Shared Buffers

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Solution Overview

Problem

Existing optical receivers in lidar systems face challenges in efficiently aggregating data from multiple photodetectors without the need for shared memory buffers, leading to increased latency and storage requirements.

Innovation Solution

A multi-chip daisy-chain configuration where each processor outputs processed data to a common data pipeline in an out-of-order manner, allowing for efficient data injection without buffering, using a shared clock to synchronize the chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a shared memory buffer is used to aggregate data from multiple photodetectors, then data aggregation reliability is improved, but latency and storage requirements increase

Engineering Contradiction:
Improvedata aggregation reliabilityVSAvoidprocessing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the data aggregation system into multiple independent processing pipelines, each handling data from specific photodetectors. Instead of using a single shared memory buffer, the system segments the aggregation process into parallel paths that feed into a combined output, eliminating the need for centralized buffering while maintaining data integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary data structure that allows processors to write to predetermined locations in a shared output buffer without requiring traditional memory buffering mechanisms. This intermediary approach enables direct data injection from multiple processors into a unified data stream, reducing latency while ensuring reliable aggregation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a shared memory buffer is used to aggregate data from multiple photodetectors, then data aggregation reliability is improved, but storage requirements increase

Engineering Contradiction:
Improvedata aggregation reliabilityVSAvoidstorage requirements
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments the data aggregation process into multiple independent pipelines, each with its own processing path. This segmentation eliminates the need for a large shared memory buffer, as each pipeline processes and outputs data independently, reducing overall storage requirements while maintaining aggregation reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary organization of data paths and predetermined output locations, allowing processors to directly inject data into the final output buffer without intermediate buffering. This preliminary structuring of data flow eliminates the need for additional storage resources that would otherwise be required for temporary buffering.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If processors output data in a predetermined order to a common data pipeline, then data stream completeness is improved, but device complexity increases

Engineering Contradiction:
Improvedata stream completenessVSAvoiddata pipeline complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple processor outputs into a single common data pipeline by assigning predetermined output locations for each processor. This merging approach ensures that all data streams are combined into a complete, ordered output stream without requiring complex coordination or additional control logic, thus improving data completeness while limiting complexity growth.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12372629B2Multi-chip daisychain for output aggregation
Publication Date: 2025.07.29 WAYMO LLC
  • US12372629B2 patent drawing
  • US12372629B2 patent drawing
  • US12372629B2 patent drawing

AI summary

An optical receiver may include a plurality of photodetectors, a common processed data pipeline, and a plurality of processors. Outputs of the plurality of processors are communicatively coupled to the common processed data pipeline. Each processor is configured to accept input signals from a respective photodetector of the plurality of photodetectors. Each processor is also configured to process the input signals to provide processed data and output the processed data into a data stream of the common processed data pipeline according to one or more predetermined data locations. A method for using the optical receiver and a non-transitory computer readable medium are also described.