Daisy Chain Persistent Memory Modules for Storage Latency Reduction
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Solution Overview
Problem
Current data storage systems face limitations in reducing latency and increasing bandwidth when using NAND Flash memory, as most CPUs support only a limited number of persistent memory modules via DIMM slots, leading to inadequate storage capacity and high latency.
Innovation Solution
A computer subsystem design featuring a CPU connected to byte-addressable memory modules and persistent memory modules in a daisy chain configuration via memory channels, allowing for efficient data management and storage through a master/slave interface, which reduces latency and enhances storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND Flash memory is connected to CPUs via traditional SATA/SAS interfaces, then storage capacity is provided, but latency increases and bandwidth is limited
Solution Approach 1:
The storage system is segmented into multiple persistent memory modules that can be independently connected to the CPU via separate memory channels. Each module operates as an independent unit with its own controller, allowing parallel data access and reducing the latency penalty associated with traditional sequential storage interfaces.
Solution Approach 2:
The patent transitions from traditional 2D storage interfaces (SATA/SAS) to a 3D memory architecture where persistent memory modules are vertically stacked and connected through the memory bus. This dimensional change enables simultaneous access to multiple storage units through the memory channel, dramatically increasing bandwidth and reducing latency while maintaining high storage capacity.
2Quantity of substance
If multiple persistent memory modules are connected via DIMM slots, then storage capacity increases, but CPU support limitations reduce the number of available slots
Solution Approach 1:
The persistent memory modules are designed with universal compatibility, allowing the same module design to be used across multiple CPU platforms. The modules incorporate standardized interfaces and controllers that can operate with different CPU architectures, maximizing the number of supported modules per CPU while maintaining high storage capacity.
Solution Approach 2:
The system employs a nested architecture where multiple persistent memory modules are organized in hierarchical tiers. Primary memory modules are directly attached to the CPU, while secondary modules are connected through intermediate controllers. This nesting enables the CPU to access a large total capacity through a limited number of physical slots by aggregating data from multiple hierarchical levels.
3Quantity of substance
If all DIMM slots are populated to maximize storage capacity, then storage capacity increases, but memory speed decreases
Solution Approach 1:
Different persistent memory modules are assigned different functional characteristics based on their position in the hierarchy and their connection to specific memory channels. Modules with faster access speeds are positioned for critical operations, while modules with higher capacity are optimized for bulk storage. This local differentiation allows the system to maintain high overall performance while achieving maximum storage capacity through strategic module placement and configuration.
Data Source
AI summary
The present invention is directed to a computer subsystem that includes a central processing unit (CPU); one or more byte-addressable memory modules having a dual in-line memory module (DIMM) form factor connected to the CPU via a first memory channel; and a master persistent memory module and one or more slave persistent memory modules having the DIMM form factor connected to the CPU via a second memory channel. The master persistent memory module and the one or more slave persistent memory modules are connected in a daisy chain configuration. The one or more slave persistent memory modules receive commands directly from the master persistent memory module.