Daisy-Chain Seal Ring Structure for Wafer Crack Resistance

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Solution Overview

Problem

Existing seal ring structures in semiconductor devices are inadequate in preventing wafer cracking during cutting or sawing, especially when wafers are stacked and bonded, leading to reliability issues and contamination risks.

Innovation Solution

A daisy chain seal ring structure is introduced, comprising metal structures in both wafers with metal bonding elements that form a series of coupled metal structures, reducing stress and improving contamination prevention by incorporating a test pattern and trench structures for enhanced reliability and manufacturing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional seal ring structure is used, then the device provides basic sealing, but wafer cracking occurs during cutting or sawing when wafers are stacked and bonded

Engineering Contradiction:
Improvewafer cracking preventionVSAvoidstress resistance during sawing
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The seal ring structure is divided into multiple discrete metal structures arranged in a daisy chain configuration. Each metal structure is separated from others by gaps, allowing independent stress management. This segmentation enables the structure to accommodate thermal expansion and mechanical stress during sawing operations, preventing wafer cracking while maintaining sealing effectiveness.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If wafers are stacked and bonded to increase device complexity, then more functionality is achieved, but stress during cutting increases leading to wafer cracking

Engineering Contradiction:
Improvedevice functionalityVSAvoidwafer integrity during processing
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The daisy chain seal ring structure acts as an intermediary element between stacked wafers. The metal structures provide mechanical coupling and stress distribution across the wafer stack, while the gaps between structures allow for thermal expansion and stress relief. This intermediary structure enables multi-wafer stacking for enhanced functionality while protecting against stress-induced cracking during processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Strength

If the seal ring structure is made more robust to prevent cracking, then stress resistance improves, but contamination prevention capability decreases

Engineering Contradiction:
Improvestress resistanceVSAvoidcontamination risk
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The seal ring structure implements different local qualities: the metal structures provide robust mechanical strength and stress resistance, while the gaps between structures maintain contamination prevention pathways. Each segment is optimized for its specific function - the solid metal portions handle mechanical stress, while the gap regions allow for controlled contamination barriers. This local differentiation resolves the contradiction between strength and contamination prevention.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12170234B2Daisy-chain seal ring structure
Publication Date: 2024.12.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12170234B2 patent drawing
  • US12170234B2 patent drawing
  • US12170234B2 patent drawing

AI summary

A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.