Daisy Chain Storage Latency Determination

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Solution Overview

Problem

Conventional daisy chain systems face high latencies and complex control mechanisms due to large buffer sizes and scheduling complexities, making it difficult to determine exact latency without artificial limitations.

Innovation Solution

A storage system with a master controller that determines individual latency for each storage node based on upstream communication buffer constraints, burst length, clock frequency, and bus width, prioritizing responses from nodes further down the chain to minimize latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional daisy chain systems use large buffer sizes and scheduling algorithms to manage memory access, then system reliability is improved, but latency increases and device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-determining latency values for each storage node in the daisy chain during system initialization or configuration. The master controller stores these pre-calculated latency values and uses them directly when managing memory access, eliminating the need for complex real-time scheduling algorithms. This approach maintains system reliability through proper buffer management while significantly reducing latency by using predetermined timing information.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If conventional daisy chain systems use complex scheduling algorithms to manage memory access, then system reliability is improved, but device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the complex scheduling algorithm from the system and replaces it with a simpler latency-based management approach. By removing the need for complex real-time scheduling and using predetermined latency values instead, the system maintains reliability through proper buffer management while significantly reducing control mechanism complexity. The master controller simply uses the pre-determined latency values to manage memory access without requiring sophisticated scheduling logic.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If conventional daisy chain systems use large buffer sizes to manage data flow, then system reliability is improved, but loss of time increases due to buffer management overhead

Engineering Contradiction:
Improvesystem reliabilityVSAvoidbuffer management overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by using pre-determined latency values as a new parameter to control memory access timing. Instead of relying on large buffer sizes and complex scheduling, the system changes the approach to use fixed latency parameters that are calculated in advance. This allows the system to maintain reliability with smaller buffers while reducing the time lost to buffer management overhead, as the predetermined latency values provide clear timing guidance for data transfer operations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8930593B2Method for setting parameters and determining latency in a chained device system
Publication Date: 2015.01.06 SPANSION LLC
  • US8930593B2 patent drawing
  • US8930593B2 patent drawing
  • US8930593B2 patent drawing

AI summary

A storage system and method for setting parameters and determining latency in a chained device system. Storage nodes store information and the storage nodes are organized in a daisy chained network. At least one of one of the storage nodes includes an upstream communication buffer. Flow of information to the storage nodes is based upon constraints of the communication buffer within the storage nodes. In one embodiment, communication between the master controller and the plurality storage nodes has a determined maximum latency.