Daisy-Chained Electrode Driver ICs for Synchronized Neurostimulation
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Solution Overview
Problem
Current implantable neurostimulator systems face challenges in efficiently managing and synchronizing the stimulation pulses across multiple electrode-driver integrated circuits, leading to potential charge imbalances and inefficiencies in therapy delivery.
Innovation Solution
The implementation of a daisy-chained architecture using two identical electrode-driver ICs, where one IC acts as a master and the other as a slave, connected via a centralized bus with additional control signals, allows for simultaneous stimulation pulse delivery and voltage monitoring across electrodes, ensuring synchronized therapy and reducing power consumption by selectively enabling clocks as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple electrode-driver ICs are used to increase electrode capacity, then the number of electrodes is improved, but synchronization and charge balance between ICs deteriorates
Solution Approach 1:
The system is divided into multiple identical electrode-driver ICs (master and slave), each capable of independently driving electrodes. This segmentation allows the system to scale electrode capacity while maintaining standardized interfaces and control protocols between modules.
Solution Approach 2:
The master IC receives feedback signals from the slave IC including charge balance information and synchronization status. This feedback mechanism enables the master IC to adjust stimulation parameters and maintain proper charge balance across all electrodes driven by different ICs.
2Reliability
If a centralized bus with additional control signals is implemented to manage multiple ICs, then communication and synchronization are improved, but device complexity increases
Solution Approach 1:
The centralized bus is designed with multi-functional control signals that serve multiple purposes: chip select for IC identification, clock signal for synchronization, and charge balance control for therapy coordination. This universal bus structure reduces the need for separate dedicated signal lines for each function.
Solution Approach 2:
The bus interface allows dynamic parameter changes including enabling/disabling individual ICs, adjusting clock frequencies, and modifying charge balance parameters. This flexibility enables the system to adapt to different therapeutic configurations without requiring hardware changes.
3Use of energy by moving object
If clocks are selectively enabled only when needed, then power consumption is reduced, but timing coordination between ICs deteriorates
Solution Approach 1:
The clock signal is implemented as a periodic signal that can be selectively enabled and disabled. The master IC controls the clock timing, enabling it only when data transmission or synchronization operations are required, and disabling it during idle periods to conserve power in the slave IC.
Solution Approach 2:
The master IC performs preliminary coordination by anticipating when the slave IC will need to be active. Control signals are prepared in advance to enable the slave IC's clock just before data transmission is needed, ensuring timing coordination is maintained while minimizing the duration of active clock signaling.
Data Source
Figure 1A~1B
Figure 2
Figure 3A
AI summary
Architectures for an implantable neurostimulator system having a plurality of electrode-driver integrated circuits (ICs) in provided. Electrodes from either or both ICs can be chosen to provide stimulation, and one of the IC acts as the master while the other acts as the slave. A parallel bus operating in accordance with a communication protocol couples the ICs, and certain functional blocks not needed in the slave are disabled. Stimulation parameters are loaded via the bus into each IC, and a stimulation enable command is issued on the bus to ensure simultaneous stimulation from the electrodes on both ICs. Clocking strategies are also disclosed to allow clocking of the master and slave ICs to be independently controlled, and to ensure that relevant internal and bus clocks used in the system are synchronized.