Daisy Chained Self Timed Memory Chips Buffer Elimination
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Solution Overview
Problem
Existing memory systems require buffer chips that consume area, power, and increase costs, and involve complex signaling paths due to the need for point-to-point interconnections and multidrop connections, which complicates electronic packaging and system design.
Innovation Solution
A computer system with a memory controller and a daisy chain of self-timed memory chips, where the memory controller transmits address/command words through a chain of unidirectional links, eliminating the need for buffer chips by using point-to-point interconnections between memory chips, and implementing self-timed access control using ring oscillators and bit line charging/discharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer chips are used in memory systems with point-to-point interconnections, then reliable data transmission is achieved, but area consumption increases
Solution Approach 1:
The patent removes buffer chips from the memory system architecture entirely. Instead of using buffer chips to manage point-to-point interconnections, the system employs a daisy-chained topology where memory chips directly interface with each other through controlled impedance traces on the PCB, eliminating the need for separate buffer chip components and their associated area consumption.
Solution Approach 2:
The patent merges the functions of buffer chips into the memory chips themselves. Each memory chip incorporates input buffers and output buffers internally, allowing it to directly drive and receive signals on the daisy-chain interconnection without requiring external buffer chips. This integration eliminates redundant components and reduces overall system area.
2Reliability
If buffer chips are used in memory systems, then signal buffering is provided, but power consumption increases
Solution Approach 1:
The patent extracts the buffer function from separate buffer chip components and eliminates the need for dedicated buffer chips in the memory system. The buffering capability is retained through internal buffers within each memory chip, which are only activated when needed for data transmission, thereby reducing continuous power consumption associated with external buffer chips.
Solution Approach 2:
Each memory chip serves its own buffering needs through internally integrated buffers. The memory chips autonomously manage their own signal driving and receiving capabilities without requiring external buffer chips, thereby eliminating the continuous power consumption that would be required to maintain external buffer chip operation.
3Reliability
If buffer chips are used for memory interconnections, then data transmission is supported, but manufacturing costs increase
Solution Approach 1:
The patent removes buffer chips from the bill of materials and assembly requirements. By eliminating these additional components, the system reduces component count, simplifies assembly procedures, and lowers overall manufacturing costs while maintaining data transmission capabilities through direct daisy-chained connections between memory chips.
4Adaptability or versatility
If multidrop connections are used in memory systems, then complex signaling paths are created, but connection flexibility is improved
Solution Approach 1:
The patent segments the memory system into individual memory chip units that are daisy-chained in series. Each memory chip is a self-contained module with integrated buffers and control logic, allowing for modular assembly and flexible configuration. The segmentation creates simple, direct signaling paths between adjacent chips rather than complex multidrop connections, while maintaining connection flexibility through the modular daisy-chain architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces area and power consumption, simplifies circuitry, and enhances memory system efficiency by eliminating buffer chips and optimizing data transmission through self-timed access control, thereby improving memory access times and system performance.
Implementation Method 1
access timing of the array is controlled by a self time block on the memory chip, the self time block determining one or more access timings at which the array will operate
Implementation Method 2
a bit line configured to be charged and discharged that is part of the ring oscillator
Data Source
AI summary
A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.