Daisy-Chained Memory Bus Architecture for Throughput and Latency
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Solution Overview
Problem
Existing memory architectures face limitations in throughput due to signal reflections from multi-drop connections and increased complexity and cost with wider word widths, while Fully Buffered Dual In-Line Memory Modules introduce latency and design complexity.
Innovation Solution
A point-to-point data bus and daisy-chained address bus architecture that allows direct connections between memory components and a memory controller, enabling flexible configuration and reduced latency, with each memory component having a fraction of the pin count and data interface width of the controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-drop connections are used from memory controller to memory components, then pin count is reduced, but signal reflections occur which limit throughput and high frequency operation
Solution Approach 1:
The patent segments the memory system into multiple independent point-to-point connections between the memory controller and memory components. Instead of a single multi-drop connection, the system uses multiple dedicated connections that can operate independently at high frequencies without signal reflections, thereby maintaining high throughput while reducing the need for excessive pins through efficient use of each connection.
2Quantity of substance
If word width is increased to expand memory capacity, then storage capacity increases, but routing complexity increases and data misalignment occurs which frustrates high frequency operation
Solution Approach 1:
The patent divides the wide data bus into multiple narrower point-to-point connections. Each connection handles a portion of the data width, allowing for simpler routing that maintains signal integrity at high frequencies. The memory controller and memory components process data across these segmented connections in parallel, achieving high capacity without the routing complexity and data misalignment issues of a single wide bus.
Solution Approach 2:
The patent transitions from a single-dimensional wide bus approach to a multi-dimensional point-to-point connection architecture. Data is transmitted across multiple independent connection dimensions simultaneously, effectively increasing capacity while keeping each individual connection simple and manageable for high-frequency operation.
3Quantity of substance
If word width is increased to expand memory capacity, then storage capacity increases, but pin count increases which adds to manufacturing cost
Solution Approach 1:
The patent segments the data path into multiple point-to-point connections with manageable pin requirements. This approach achieves high memory capacity through efficient use of pins across multiple connections, rather than requiring a single wide bus with excessive pins, thereby reducing manufacturing costs while maintaining high capacity.
4Quantity of substance
If FB-DIMM architecture with Advanced Memory Buffer is used, then pin count on memory controller is reduced, but latency increases due to buffering and queue processing
Solution Approach 1:
The patent extracts and eliminates the Advanced Memory Buffer component from the FB-DIMM architecture. By removing the buffering and queue processing stage, the system achieves direct point-to-point communication between the memory controller and memory components, thereby eliminating the latency introduced by buffering while still maintaining reduced pin count through efficient point-to-point connection design.
Solution Approach 2:
The patent removes the intermediary buffer component that caused latency. Instead of using a buffer as an intermediary between controller and memory, the system establishes direct point-to-point connections, allowing data to flow without the delays of buffering and queue processing while still managing pin count efficiently.
Data Source
AI summary
In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.