Daisy Chained Memory Controllers for Expanded Module Capacity
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Solution Overview
Problem
Current memory systems, such as those using fully buffered DIMMs, are limited in handling more than eight memory modules and lack full memory operation functionality, like atomic operations, without a separate controller chip.
Innovation Solution
A memory system with a daisy chain arrangement of memory controllers interconnected to provide address and read/write control signals, utilizing encoder/decoders to manage addresses and control signals across multiple memory modules, enabling full memory operation without a separate controller chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single memory controller is used with FB-DIMM arrangement, then the system can support up to 8 DIMMs per channel, but the system cannot support more than eight memory modules and lacks full memory operation functionality
Solution Approach 1:
The memory controller is divided into multiple segments (first memory controller and second memory controller) that are daisy-chained together. Each controller segment can independently manage a portion of the memory modules while maintaining full operational functionality. This segmentation allows the system to support more than 8 memory modules by distributing the control functions across multiple controller units.
Solution Approach 2:
The patent introduces an intermediary memory controller unit that acts as a bridge between the host and additional memory modules. This intermediary controller receives commands from the host, translates them into appropriate signals for the target memory modules, and manages the daisy-chain communication between controller segments, enabling full memory operation functionality without requiring a separate controller chip for each module.
2Quantity of substance
If FB-DIMM arrangement is used, then memory expansion is achieved, but separate controller chip is required for full memory operation functionality
Solution Approach 1:
The patent merges the functions of multiple memory controllers into a daisy-chained arrangement where controller segments are interconnected through standard memory interfaces. This consolidation eliminates the need for separate dedicated controller chips while maintaining full memory operation functionality. The merged controller system manages all memory modules through a unified control structure that distributes commands across the daisy-chain.
Solution Approach 2:
Each memory controller segment in the daisy-chain is designed with universal functionality to handle various memory operations including atomic operations, read-modify-write sequences, and standard memory access. This multi-functional design allows any controller segment to independently manage memory operations without requiring specialized separate controller chips for different operation types.
3Quantity of substance
If daisy-chain topology is used for memory expansion, then signal routing complexity increases for addresses beyond the first controller
Solution Approach 1:
The memory controller segments implement feedback mechanisms where each controller monitors incoming address signals, determines whether the target memory modules are attached to its segment or downstream segments, and dynamically routes commands accordingly. This feedback-based routing reduces signal complexity by enabling intelligent command distribution rather than requiring complex hard-wired routing for all possible address combinations.
Solution Approach 2:
The patent employs dynamic signal routing where the memory controller segments can adaptively change their operational mode based on detected memory module configurations. Each controller segment dynamically enables or disables specific signal paths based on whether memory modules are present on its attached DIMMs or if commands need to be forwarded to downstream segments, thereby reducing overall signal routing complexity.
Data Source
AI summary
A memory system having a plurality of sets of memory modules. The system includes a plurality of sets of memory controllers, each one of the memory controllers being coupled to a corresponding one of the plurality of sets of memory modules. The system includes a port for providing address and read/write control signals to the memory system. The memory controllers are interconnected in a daisy chain arrangement to the port.