Daisy-Chained Memory Modules Staggered Resume Transition

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Solution Overview

Problem

The peak current generated when a semiconductor device returns from low-power-consuming resume mode to normal mode is excessive, posing challenges in securely retaining data during operation with low voltage, especially in mobile products with increasing memory module capacities and numbers.

Innovation Solution

A semiconductor device with daisy-chained memory modules, each equipped with a switch for controlling source voltage supply and a delay circuit that receives a resume control signal and outputs a delayed signal to the next stage, allowing memory modules to transition from resume mode to normal mode at different times, thereby reducing the peak current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If all memory modules transition from resume mode to normal mode simultaneously, then the resume control is simple and fast, but the peak rush current becomes excessively large

Engineering Contradiction:
Improveresume mode transition speedVSAvoidpeak rush current
Core Design Contradiction:
SpeedVSPower

Solution Approach 1:

The patent divides the simultaneous transition of all memory modules into segmented transitions by introducing delay circuits in a daisy-chain configuration. Each memory module transitions at a different time based on the delayed resume control signal, thereby segmenting the peak current demand across multiple time points while maintaining relatively fast transition speed.

Inventive Principle:
Principle #1Segmentation

2Power

If memory modules are daisy-chained with delay circuits to reduce peak current, then the rush current is reduced, but the device complexity increases

Engineering Contradiction:
Improvepeak rush currentVSAvoidcircuit complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent merges the delay function directly into the existing memory module structure, where each memory module contains a delay circuit that processes the resume control signal. This integration approach reduces overall system complexity compared to adding separate delay components, while still achieving the current reduction benefit through daisy-chained delayed transitions.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If the capacity and number of embedded SRAMs are increased, then the memory functionality is improved, but the peak rush current during resume mode transition becomes larger

Engineering Contradiction:
Improvememory capacityVSAvoidpeak rush current
Core Design Contradiction:
Quantity of substanceVSPower

Solution Approach 1:

The patent applies segmentation by organizing multiple memory modules in a daisy-chain configuration where each module transitions from resume mode at a staggered time point. This allows the system to support increased memory capacity and quantity while preventing the peak rush current from scaling linearly with the number of modules, as the transitions are distributed across multiple time intervals.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8837238B2Semiconductor device having a plurality of memory modules
Publication Date: 2014.09.16 RENESAS ELECTRONICS CORP
  • US8837238B2 patent drawing
  • US8837238B2 patent drawing
  • US8837238B2 patent drawing

AI summary

A semiconductor device which can reduce the peak value of the rush current generated during a transition from resume mode to normal mode. The semiconductor device has a plurality of daisy-chained memory modules. Each of the memory modules includes a memory array, a switch for controlling, in resume mode, source voltage supply to a constituent element of the memory module, and a delay circuit which receives a resume control signal ordering a transition from resume mode to normal mode and outputs a resume control signal delayed from the inputted resume control signal to the memory module of the next stage.