Daisy Chained Memory System Buffer Elimination
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Solution Overview
Problem
Current memory systems require buffer chips that occupy space, consume power, and increase costs due to the need for point-to-point interconnections and multidrop connections, which also complicate signaling and diagnosis.
Innovation Solution
A memory system with a daisy chain configuration of memory chips connected via point-to-point unidirectional address/command and data bus links, eliminating the need for buffer chips by directly routing address/command words and data between memory chips, reducing complexity and space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer chips are used for point-to-point interconnections, then signaling and data transmission are enabled, but area occupation, power consumption, and device complexity increase
Solution Approach 1:
The patent removes buffer chips from the memory system architecture, extracting the intermediary component that caused complexity. Memory chips are directly interconnected through a daisy-chain topology, eliminating the need for buffer chips while maintaining data transmission capability through direct point-to-point links.
Solution Approach 2:
The patent merges the functions of address/command transmission and data transmission into a unified daisy-chain interconnection structure. Multiple memory chips are combined in series, sharing common interconnection paths while maintaining individual point-to-point communication channels, thereby reducing overall system complexity.
2Adaptability or versatility
If buffer chips are used for multidrop connections, then multiple memory chips can be accessed, but area occupation and power consumption increase
Solution Approach 1:
The patent segments the interconnection architecture into multiple daisy-chain paths, allowing different groups of memory chips to be accessed through different chains. This segmentation enables versatile access to multiple chips without requiring a single complex multidrop connection, reducing the area needed for interconnections on the carrier.
3Productivity
If buffer chips are used for interconnections, then data transmission is enabled, but power consumption increases
Solution Approach 1:
Memory chips in the daisy-chain configuration perform their own driving and receiving functions without requiring external buffer chips. Each memory chip actively participates in signal transmission to the next chip in the chain, eliminating the need for additional power-consuming buffer components while maintaining high-speed data transmission capability.
Data Source
AI summary
A memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.