Damascene Bit Line Trench Structure for Capacitance Reduction
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Solution Overview
Problem
In semiconductor devices at the 30 nm level or below, it is challenging to simultaneously achieve desirable bit line resistance and capacitance due to the trade-off between critical dimension and overlap area between bit lines and storage node contact plugs, leading to potential SAC failures and increased contact resistance.
Innovation Solution
A semiconductor device with a two-staged trench structure is implemented, where bit lines are formed in the first trench and insulating layers gap-fill the second trench between the bit line and storage node contact plugs, reducing the overlap area and capacitance while maintaining bit line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the critical dimension of the bit line is decreased to reduce overlap area, then capacitance between bit line and storage node contact plug is reduced, but bit line resistance increases
Solution Approach 1:
The bit line structure is segmented into multiple conductive layers (first conductive pattern, second conductive pattern) separated by insulating layers. This segmentation allows the bit line to maintain electrical connectivity while reducing the overlap area with storage node contact plugs, thereby decreasing capacitance without significantly increasing resistance
Solution Approach 2:
The bit line transitions from a single-plane structure to a multi-layer three-dimensional structure. By stacking conductive patterns at different vertical levels and separating them with insulating layers, the design reduces horizontal overlap area while maintaining conductive pathways, effectively lowering capacitance without compromising resistance
2Reliability
If the critical dimension of the bit line is increased to reduce resistance, then bit line resistance decreases, but overlap area increases causing increased capacitance
Solution Approach 1:
The bit line conductive material is divided into multiple patterns separated by insulating layers. This allows increasing the total conductive cross-section (reducing resistance) while the segmented arrangement reduces continuous overlap with storage node contact plugs, thereby controlling capacitance
Solution Approach 2:
Different regions of the bit line structure have different properties: conductive patterns provide low resistance pathways, while insulating layers provide electrical isolation and capacitance reduction. This local differentiation allows simultaneous optimization of resistance and capacitance characteristics
3Reliability
If storage node contact plugs are formed individually, then contact resistance can be controlled, but the process complexity increases and SAC failures may occur
Solution Approach 1:
Adjacent storage node contact plugs are formed as a merged structure and then separated through the damascene process. This merging approach simplifies the formation process, ensures proper spacing and alignment, and maintains controlled contact resistance while reducing process complexity compared to individual formation
Data Source
AI summary
A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.