Damascene Process for Semiconductor Contact Plug Formation
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Solution Overview
Problem
As semiconductor integration density increases, the area for forming storage node contact plugs decreases, making the bit line patterning and storage node contact plug processes difficult due to limitations in mask photolithography, particularly in forming high storage node contact plugs without a hole-type contact mask.
Innovation Solution
A method for fabricating semiconductor devices that forms bit lines and storage node contact plugs using a damascene process without a bit line patterning process or a hole-type contact mask, involving the creation of isolation and sacrificial patterns, trenches, and conductive lines, allowing for the formation of plugs in contact holes without the need for a hole-type contact mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If mask photolithography is used for bit line patterning and storage node contact plug formation, then conventional manufacturing processes can be applied, but manufacturing precision and reliability deteriorate due to limitations in forming high contact plugs in reduced areas
Solution Approach 1:
The patent extracts and eliminates the hole-type contact mask from the manufacturing process. Instead of using a separate contact mask for defining storage node contact holes, the method uses the bit line pattern itself as the defining structure, thereby simplifying the process while improving precision in forming high contact plugs in reduced areas
Solution Approach 2:
The bit line pattern serves multiple functions: it acts as both the functional bit line conductor and as the defining structure for the storage node contact holes. This multi-functionality eliminates the need for a separate contact mask, resolving the contradiction between manufacturing precision and process complexity
2Productivity
If integration density of semiconductor devices is increased, then device functionality and capacity are improved, but the area for forming storage node contact plugs decreases, making the process more difficult
Solution Approach 1:
The patent transitions from a planar two-dimensional patterning approach to a three-dimensional approach where bit lines are formed with controlled heights and the storage node contact holes are defined by the bit line structure itself. This dimensional change allows for maintaining manufacturing precision even as integration density increases and contact plug areas decrease
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.