Damascene Digit Lines for Low-Leakage Stacked Memory Cells
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Solution Overview
Problem
Existing memory device fabrication techniques using vertically stacked memory cells face challenges with complex processes, multiple spacer materials, and high temperature exposure, leading to defects and electrical variations, particularly in the formation of digit lines which are prone to material degradation.
Innovation Solution
The use of damascene digit lines is introduced, where dummy digit lines are formed and replaced after cell contact formation, avoiding high temperature processes, and employing a thinner insulating material and fewer spacer layers to reduce defects and electrical leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically stacked memory cells are fabricated using existing techniques with multiple spacer materials and high temperature processes, then memory device functionality is achieved, but defects and electrical variations increase due to material degradation
Solution Approach 1:
The digit line structure is prepared in advance with placeholder materials and protective layers before the high temperature cell contact formation process. The actual digit line material is deposited after the high temperature process is complete, ensuring it never experiences the degrading thermal conditions while the placeholder structures guide subsequent fabrication steps.
Solution Approach 2:
Placeholder structures such as mandrels and sacrificial layers are introduced as intermediary elements that occupy the digit line space during high temperature processing. These intermediaries protect the final digit line material from thermal exposure while maintaining the required structural geometry, and are removed or replaced after the critical high temperature step.
2Manufacturing precision
If multiple spacer materials are used in digit line formation, then structural definition is achieved, but device complexity and defect density increase
Solution Approach 1:
The patent applies different material properties to different regions of the digit line structure. The placeholder structures use materials optimized for high temperature stability, while the final digit line material is selected for its electrical and capacitive properties. This localized material assignment achieves precise dimensional control without requiring multiple spacer layers throughout the entire structure.
Solution Approach 2:
The invention changes the temporal parameter of material deposition, placing the actual digit line material deposition after the high temperature process rather than before. This parameter change eliminates the need for thermally stable spacer materials and reduces the number of material interfaces, simplifying the overall structure while maintaining manufacturing precision through controlled deposition timing.
3Reliability
If thicker insulating materials are used in digit line formation, then electrical isolation is improved, but device area increases and capacitance performance deteriorates
Solution Approach 1:
The digit line structure employs composite material layers where a thin high-k dielectric material provides superior electrical isolation performance per unit thickness compared to conventional low-k materials. This allows achieving the required isolation levels with reduced insulating layer thickness, thereby minimizing device area while maintaining or improving electrical performance.
Data Source
AI summary
Systems, methods and apparatus are provided for damascene digit lines. For instance, a damascene digit line can be formed by forming a plurality of dummy digit lines on a semiconductor substrate that are separated by a first set of vertical trenches, depositing a sacrificial insulating material in the first set of vertical trenches, forming, and depositing an insulating fill material in, a second set of vertical trenches, forming, and depositing a nitride material in, nitride material deposition spaces; removing at least a portion of the semiconductor substrate to form plurality of cell contact deposition spaces, forming cell contacts in the cell contact deposition spaces, removing the dummy digit lines to form a plurality of vertical openings, removing nitride material to form expanded vertical opening, depositing a digit line insulating material in the expanded vertical openings to form digit line deposition spaces, and forming digit lines.