Damascene Etch Stop Layer for Single-Step Via and Trench Patterning
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability while reducing complexity, particularly in forming via and trench openings during the damascene etching process, where the existing methods face issues with process complexity and undesired removal of dielectric layers.
Innovation Solution
A method involving the use of a photomask with a translucent layer and an opaque layer to perform a single-step damascene etching process, which includes forming a patterned mask layer to create via and trench openings, and optionally employing an etch stop layer to prevent unwanted removal of dielectric layers, thereby simplifying the process and enhancing the semiconductor device's reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-step damascene etching process is used to form via and trench openings, then process complexity is reduced and productivity is improved, but undesired removal of dielectric layers occurs and manufacturing precision deteriorates
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the dielectric layers. This layer selectively stops the etching process at a precise depth, preventing undesired removal of underlying dielectric layers while enabling single-step formation of both via and trench openings. The etch stop layer acts as a mediator that reconciles the conflict between high productivity and manufacturing precision.
Solution Approach 2:
The patent utilizes changes in etch selectivity parameters by introducing materials with different etch rates. The etch stop layer is specifically chosen to have high etch selectivity compared to adjacent dielectric layers, allowing the etching process to automatically terminate at the desired depth. This parameter change enables precise depth control without requiring multiple etching steps.
2Manufacturing precision
If conventional multi-step etching processes are used to prevent undesired dielectric layer removal, then manufacturing precision is maintained, but device complexity increases and productivity decreases
Solution Approach 1:
The patent extracts the depth control function from the mask pattern and separates it into a dedicated etch stop layer. Instead of relying on complex mask designs to control etching depth for different features, the depth control is extracted and implemented through the selective etching properties of the etch stop layer. This simplifies the overall process by removing the need for multiple etching steps with different masks.
Solution Approach 2:
The etch stop layer serves multiple functions simultaneously: it acts as a depth control mechanism, a protective barrier for underlying layers, and a selective stopping point for the etching process. This multi-functionality reduces process complexity by consolidating several control mechanisms into a single layer, thereby maintaining manufacturing precision without increasing device complexity.
3Reliability
If the etch stop layer is positioned to prevent dielectric layer removal, then reliability is improved, but the structure becomes more complex
Solution Approach 1:
The etch stop layer is formed in advance during the dielectric layer stacking process, before the damascene etching step. This preliminary action ensures that the depth control mechanism is already in place, allowing the subsequent etching process to reliably stop at the correct depth without requiring additional steps. The preliminary formation of the etch stop layer improves reliability while minimizing added structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process complexity and alleviates the loading effect during etching, resulting in improved quality and reliability of semiconductor devices by allowing the formation of via and trench openings in a single step and minimizing the removal of dielectric layers.
Implementation Method 1
patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature
Implementation Method 2
performing a damascene etching process to form a via opening along the first etch stop layer and the first dielectric layer, and a trench opening in the second dielectric layer
Data Source
AI summary
The present application discloses a method for fabricating a semiconductor device. The method includes: providing a photomask comprising an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; providing a device stack comprising a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer; forming a pre-process mask layer on the device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer comprising a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature. The method also includes performing a damascene etching process to form a via opening in the first dielectric layer and a trench opening in the second dielectric layer.