Damascene Self-Aligned F-RAM Sidewall Capacitors

The patent transitions from planar capacitors to three-dimensional sidewall capacitors formed on the vertical walls of trenches. This vertical arrangement in the third dimension increases storage density while maintaining the non-volatile ferroelectric storage function. The sidewall capacitors utilize the vertical sidewalls of etched trenches as the active capacitor region, effectively using the vertical dimension to pack more storage elements per unit area.

The patent implements a nested structure where the ferroelectric capacitor is embedded within the sidewall of the trench, and the control gate is positioned above the trench. The sidewall capacitor structure nests the ferroelectric layer and electrode structures within the vertical wall of the trench, allowing compact integration. The control gate structure nests over the trench opening, creating a vertically stacked configuration that reduces lateral footprint.

The patent combines multiple functions into integrated process steps. The sidewall spacer formation serves both as a structural element defining the capacitor geometry and as a mask for subsequent etching steps. The trench etching process simultaneously creates the cavity for the sidewall capacitor and the vertical walls that form the capacitor structure. This merging of functions reduces the total number of discrete processing steps and masks required.

The patent performs preliminary actions in the process sequence to simplify subsequent steps. The oxide layer is deposited and patterned first to define the trench location and geometry before any capacitor formation. The sidewall spacers are formed early to establish the capacitor footprint and serve as self-aligned masks. These preliminary structuring steps create a self-aligned framework that guides subsequent material deposition and patterning, reducing the need for additional alignment-critical masks.

The sidewall spacers serve as self-aligned structures that automatically define the capacitor geometry based on the trench dimensions. The spacer width, determined by conformal deposition thickness, directly sets the capacitor plate dimensions without requiring separate patterning steps. This self-service approach allows the structure to define its own critical dimensions through the physics of conformal film deposition, simplifying the relationship between process parameters and final device geometry.

The patent controls storage density by adjusting the thickness parameter of the conformally deposited spacer and electrode layers. By varying the deposition thickness, the capacitor dimensions and thus the storage capacity are directly controlled. This parameter-based control replaces complex geometric patterning with simple thickness control, making the device structure easier to manufacture while maintaining high storage density.