Damascene Thin-Film Resistor Single-Mask Integration
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Solution Overview
Problem
The existing methods for manufacturing copper interconnects in semiconductor devices are complex and costly, particularly when integrating thin-film resistors, which often require multiple photo lithography masks and result in resistors with high resistance variations and temperature sensitivity.
Innovation Solution
A method for manufacturing a low-cost, single-mask-layer Damascene thin-film resistor that can be integrated into copper interconnects, using a dielectric barrier layer, a hard mask, and a thin-film resistor material like TaN or SiCr, with a CMP process to create stable resistors compatible with existing copper processes, reducing mask layers and ensuring consistent resistance across a wide temperature range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional photoresist masking and plasma etching are used for copper interconnect manufacturing, then the process complexity and cost increase significantly, but the manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent combines the thin-film resistor formation process with the copper interconnect Damascene process into a single integrated flow. The resistor material is deposited concurrently with the copper fill process, and a single etch step patterns both the copper interconnect and the thin-film resistor simultaneously, eliminating the need for separate masking and etching steps that would otherwise be required for resistor fabrication.
Solution Approach 2:
The single etch process serves multiple functions: it patterns the copper interconnect lines, defines the thin-film resistor geometry, and creates the necessary trenches for dielectric filling. This multi-functional approach replaces what would traditionally require separate photolithography masking steps for each feature type, reducing process complexity while maintaining precision.
2Manufacturing precision
If multiple photo lithography mask layers are added to create thin-film resistors, then the manufacturing precision improves, but the device complexity and cost increase
Solution Approach 1:
The patent merges the resistor pattern definition with the copper interconnect patterning by using the same photoresist mask and etch process for both features. The resistor material is deposited over the entire wafer surface, and the single etch step selectively removes material to define both the copper traces and resistor regions simultaneously, eliminating the need for additional mask layers.
Solution Approach 2:
The thin-film resistor material is deposited in advance during the copper interconnect formation process, before final patterning. This preliminary deposition ensures that the resistor material is already in place and properly positioned, allowing the subsequent single etch step to define both copper and resistor features with high precision without requiring separate masking operations.
3Ease of manufacture
If poly resistors are created through ion implantation and diffusion, then the manufacturing process is simple, but the reliability and temperature stability worsen due to high resistance variations and temperature sensitivity
Solution Approach 1:
The patent changes the material parameter from polysemiconductor to thin-film metal or conductive oxide, which fundamentally alters the temperature coefficient of resistance. The thin-film resistor material exhibits near-zero TCR, providing stable resistance values over wide temperature ranges while maintaining compatibility with the copper interconnect fabrication process.
Solution Approach 2:
The patent uses composite material structures combining thin-film resistor materials (such as metal oxides or metallic films) with the copper interconnect system. The thin-film resistor layer is deposited on top of the dielectric barrier, creating a composite structure that achieves both manufacturing simplicity and superior electrical stability.
4Device complexity
If a single mask layer is used for Damascene thin-film resistor manufacturing, then the cost and device complexity reduce, but the manufacturing precision may worsen
Solution Approach 1:
The patent applies local quality by using the same etch process with different selectivities for different materials. The etch chemistry is optimized to etch the dielectric barrier at a different rate than the thin-film resistor material, allowing precise definition of resistor features even with a single mask layer. The etch stopping layer provides localized protection to ensure accurate trench depth control.
Solution Approach 2:
The patent introduces a dielectric barrier layer as an intermediary between the copper interconnect and the thin-film resistor. This barrier layer serves as an etch stop and provides a well-defined interface that enhances the precision of the single etch step, allowing accurate definition of both copper and resistor features without requiring multiple masks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and provides thin-film resistors with stable and accurate resistance values, enhancing semiconductor chip performance, especially in precision analog circuits by eliminating the need for multiple mask layers and achieving a Temperature Coefficient of Resistance close to 0.
Implementation Method 1
Copper diffusion barrier layer (typically Ta, TaN, or bi-layer of both) is deposited
Implementation Method 2
Chemical-mechanical planarization (CMP) process is then used to remove any excessive copper and barrier
Implementation Method 3
bulk Copper fill, typically through Electro-Chemical Plating process
Implementation Method 4
patterning dielectric materials, such as silicon dioxide, or fluorosilicate glass (FSG), or organo-silicate glass (OSG) with open trenches
Implementation Method 5
traditional photoresist masking and plasma etching used for aluminum interconnect
Data Source
AI summary
Disclosed is a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module including the steps of: depositing a dielectric barrier layer (100) across at least two structures (90a, b); depositing a second dielectric layer (110) atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist (120a, b) from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material (120) into the trench and bridging across the resulting at least two exposed copper surfaces.