Nanoscale Damascene Sidewall-Defined Memory Cell
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory technologies face challenges in achieving sub-lithographic dimensions and uniform electrical characteristics, with high manufacturing costs and limited integration density due to complex processes and voltage requirements for filament formation.
Innovation Solution
A non-volatile memory device with a conductive liner in trenches and a dual top electrode structure, where the thickness of the conductive liner determines the memory cell dimensions, allowing for sub-lithographic feature sizes and uniform electrical characteristics, and a method to tune these dimensions without lithographic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gate transistors are used for non-volatile memory, then data storage capability is achieved, but manufacturing process complexity and cost increase significantly
Solution Approach 1:
The patent extracts the complex floating gate transistor structure and replaces it with a simplified filament-based memory cell consisting of an electrochemically active electrode, insulating material, and top electrode. This extraction eliminates the need for complex lithographic patterning and multiple etching steps while maintaining non-volatile data storage capability through filament formation and rupture mechanisms.
Solution Approach 2:
The patent employs a disposable electrochemically active electrode material (such as copper or silver) that is intentionally designed to be consumed during operation. The material migrates to form conductive filaments and is gradually depleted, providing a simple, low-cost alternative to durable but complex floating gate structures.
2Reliability
If floating gate transistors are used, then non-volatile memory function is achieved, but uniformity of electrical characteristics deteriorates
Solution Approach 1:
The patent employs a self-organizing mechanism where the electrochemically active electrode material automatically migrates through the insulating material under applied voltage to form conductive filaments. This self-service process eliminates the need for complex lithographic patterning and results in highly uniform filament formation and rupture characteristics across all memory cells on a chip.
3Reliability
If tunneling effect is used for write/erase operations, then non-volatile data storage is achieved, but insulation damage occurs limiting write/erase cycles
Solution Approach 1:
The patent intentionally uses a consumable electrochemically active electrode material that migrates to form filaments and is gradually depleted over write/erase cycles. This disposable material approach replaces the tunneling mechanism that causes insulation damage with a controlled material migration process that naturally limits write/erase cycles through material depletion rather than insulation degradation.
4Reliability
If high voltage is applied for filament formation, then conductive filaments are created, but current supply during manufacture becomes critical
Solution Approach 1:
The patent employs electrochemical migration mechanisms that operate at significantly lower voltages compared to direct Joule heating filament formation. The electrochemical process enables filament creation through ion migration and deposition at reduced voltage levels, eliminating the high voltage and critical current supply requirements while maintaining reliable filament formation.
5Productivity
If lithographic processes are used for device scaling, then integration density increases, but minimum feature dimensions are limited by exposure resolution
Solution Approach 1:
The patent replaces the mechanical lithographic patterning process with an electrochemical field-driven migration mechanism. The conductive filaments form through electrochemical migration of active electrode material under applied voltage fields, enabling sub-lithographic feature dimensions and higher integration densities without being constrained by optical exposure resolution limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high integration density and stable, compact non-volatile memory cells with reduced voltage requirements and improved uniformity, capable of billions of set and reset cycles without degradation, and is applicable to various memory cell technologies.
Implementation Method 1
an electrochemically active electrode such as copper or silver migration within an insulating material to form conductive filaments of the active electrode material
Implementation Method 2
the filament is formed by oxygen vacancy motions. In this mechanism, the oxygen vacancies can agglomerate at grain boundaries within a metal oxide insulator and locally create metal-rich filaments
Implementation Method 3
they can be ruptured by joule heating in response to a high current
Data Source
AI summary
An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.