Damascene Template Fabrication Without CMP
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Solution Overview
Problem
Conventional silicon wafer-based manufacturing technologies for nanomaterials face limitations such as size accuracy, high cost, and non-uniformity in surface geometry, particularly when using chemical mechanical planarization (CMP) for damascene template fabrication, leading to defects like 'dishing' and 'erosion' and edge exclusion zones.
Innovation Solution
The development of improved methods for fabricating damascene templates using precise lithography and etching techniques to create raised conductive metal features and an interspersed insulating layer, resulting in a planar surface with equal electric potential and reduced non-uniformity, avoiding the need for CMP and its associated defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical mechanical planarization (CMP) is used to achieve flat topography of template surface, then flat surface is obtained, but surface non-uniformity and edge exclusion zones are created
Solution Approach 1:
The patent extracts and removes the problematic CMP process from the fabrication sequence, replacing it with an alternative approach using lithography and etching that achieves flat topography without creating edge exclusion zones or surface non-uniformity
Solution Approach 2:
Instead of using CMP to remove material and create flat surfaces (which causes edge effects), the patent inverts the approach by using lithographic patterning and etching to create raised conductive features that inherently provide the required flat topography and uniform electric potential
2Shape
If CMP is used for large area templates, then flat surface is achieved, but dishing and erosion defects occur
Solution Approach 1:
The patent replaces the mechanical CMP process with a chemical/physical lithography and etching process, substituting mechanical abrasion with photochemical patterning and selective etching that does not produce dishing or erosion defects
Solution Approach 2:
The patent changes the fabrication parameters by using controlled lithographic exposure and etching conditions to create uniformly raised conductive features, replacing the variable-pressure CMP process that causes parameter non-uniformity across large areas
3Shape
If CMP is used to achieve uniform flat surface, then planarity is improved, but edge exclusion zones are created reducing usable area
Solution Approach 1:
The patent performs preliminary lithographic patterning and etching to create raised conductive features before transfer, ensuring that the entire template surface including edges achieves uniform electric potential and flat topography without requiring post-CMP processing that would create edge exclusion zones
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new method produces damascene templates with significantly diminished surface non-uniformity and edge exclusion zones, enabling efficient and uniform electrophoretic assembly and transfer of nanoelements across larger areas without the limitations of CMP, enhancing productivity and scalability.
Implementation Method 1
depositing an adhesion layer onto the substrate; depositing a conductive metal layer onto the adhesion layer; depositing a chromium mask layer onto the resist layer
Implementation Method 2
performing lithography to create a two-dimensional pattern of voids in the resist layer
Implementation Method 3
depositing a chromium mask layer onto the resist layer such that the voids are filled with chromium to form chromium nanostructures
Implementation Method 4
etching the conducive metal layer which is not covered by the chromium nanostructures, leaving raised conductive metal features
Implementation Method 5
depositing an insulating layer onto the surface resulting from step (h) such that the chromium nanostructures and exposed conductive metal surfaces in regions between the raised conductive metal features are covered with the insulating layer
Implementation Method 6
etching to remove the chromium nanostructures and portions of the insulating layer covering the chromium nanostructures, giving rise to the damascene template
Data Source
AI summary
Methods of fabricating a damascene template for electrophoretic assembly and transfer of patterned nanoelements are provided which do not require chemical mechanical polishing to achieve a uniform surface area. The methods include conductive layer fabrication using a combination of precision lithography techniques using etching or building up the conductive layer to form raised conductive features separated by an insulating layer of equal height.