Etch Stop Removal for Capacitance Reduction in Damascene Top Via
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional interconnect structure fabrication in semiconductor ICs faces challenges such as increased capacitance due to electrical interactions between metal lines, high-k etch stop layers, and dielectric layers, and defects in dielectric layers caused by trench and fill operations, leading to variations in dielectric constant values.
Innovation Solution
A method that excludes the conventional high-k etch stop layer between dielectric layers, forming a replacement dielectric layer after creating conductive vias to embed them, thereby reducing or eliminating undesirable capacitance effects and maintaining a targeted dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high-k etch stop layer is used between dielectric layers, then etch selectivity and process control are improved, but capacitance increases due to electrical interactions between metal lines, etch stop layer, and dielectric layers
Solution Approach 1:
The patent removes the high-k etch stop layer from the interconnect structure, extracting the harmful capacitive effect source while maintaining etch selectivity through alternative means such as adjusting dielectric layer compositions or using different etch chemistry that provides sufficient selectivity without requiring a high-k etch stop layer
Solution Approach 2:
The patent changes the dielectric constant parameter of the etch stop layer by replacing high-k material with low-k material, thereby reducing capacitance while maintaining adequate etch selectivity through the low-k dielectric properties and process optimization
2Ease of manufacture
If trench and fill operations are performed to form conductive vias, then interconnect formation is achieved, but defects are introduced in dielectric layers causing variations in dielectric constant values
Solution Approach 1:
The patent performs preliminary planning of via locations and dimensions before trench formation, optimizing the trench geometry and fill process to minimize dielectric layer disruption, and using pre-formed masks or self-aligned approaches to reduce defects and maintain dielectric constant uniformity
Solution Approach 2:
The patent uses mandrel-based approaches where a temporary structure is formed, copied onto the dielectric layer to define via locations, and then removed, allowing precise via formation without extensive trench and fill operations that would disrupt dielectric uniformity
Data Source
AI summary
A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.