Damascene Wiring Equipotential Structure for TDDB Reliability

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Solution Overview

Problem

The miniaturization of semiconductor integrated circuits leads to reduced time-dependent dielectric breakdown (TDDB) lifetime and increased yield reduction due to short-circuits between fine wirings in semiconductor devices with damascene wiring, primarily caused by conductive foreign substances from metal organic residues adhering to the wiring layer during the chemical mechanical polishing (CMP) step.

Innovation Solution

Structuring fine wirings adjacent to a wide wiring with the same electric potential, ensuring a spacing of less than 0.5 μm between them, which mitigates the adherence of conductive foreign substances and prevents short-circuits, thereby maintaining TDDB lifetime and yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the wiring pitch and distance between fine wirings are reduced to increase integration level, then the integration level increases, but the TDDB lifetime between fine wirings is reduced and short-circuit risk increases

Engineering Contradiction:
Improveintegration levelVSAvoidTDDB lifetime
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies equipotentiality by making adjacent fine wirings (second and third wirings) have the same electric potential. This is achieved by connecting them to the same potential source or ground, eliminating potential differences between closely spaced wirings. This principle directly resolves the contradiction by preventing TDDB and short-circuits while allowing minimal wiring pitch, thus maintaining both high integration level and reliability.

Inventive Principle:
Principle #12Equipotentiality

2Productivity

If the wiring pitch and distance between fine wirings are reduced to increase integration level, then the integration level increases, but the yield is reduced due to short-circuits

Engineering Contradiction:
Improveintegration levelVSAvoidyield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By making the second and third wirings have the same electric potential, the patent eliminates the risk of short-circuits between these wirings. This equipotential connection ensures that even when wiring pitch is minimized for high integration, the yield is protected because no current can flow between equipotential conductors, preventing short-circuit failures.

Inventive Principle:
Principle #12Equipotentiality

3Ease of manufacture

If damascene wiring process is used with CMP step, then the wiring layer can be formed, but conductive foreign substances from metal organic residues adhere to the wiring layer surface

Engineering Contradiction:
Improvewiring layer formationVSAvoidconductive foreign substances
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful effect of conductive foreign substances into a beneficial outcome by using the equipotential configuration. Instead of trying to completely eliminate the foreign substances (which would require complex additional processing), the invention accepts their presence but neutralizes their harmful effect by ensuring that any foreign substances between the second and third wirings do not cause short-circuits because both wirings are at the same potential. This approach maintains ease of manufacture while eliminating the harm.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses the reduction of TDDB lifetime and yield reduction by ensuring that even when conductive foreign substances adhere, they do not cause short-circuits between the fine wirings, enhancing the reliability and performance of semiconductor devices.

Implementation Method 1

the damascene process requires a surface planarization step of chemical mechanical polishing (CMP) as an essential step

Methodology Applied
Scientific EffectChemical mechanical polishing:

Data Source

PatentUS8426975B2Semiconductor device having wiring layer with a wide wiring and fine wirings
Publication Date: 2013.04.23 RENESAS ELECTRONICS CORP
  • US8426975B2 patent drawing
  • US8426975B2 patent drawing
  • US8426975B2 patent drawing

AI summary

Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 μm; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 μm from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 μm from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.