Semiconductor Damascene Wiring for Exposure-Limited Miniaturization
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Solution Overview
Problem
Existing semiconductor devices face challenges in miniaturizing wiring due to limitations in exposure technology, particularly when dimensions exceed the maximum exposure region of conventional exposure apparatuses, leading to inefficiencies in manufacturing damascene structures.
Innovation Solution
The semiconductor device employs a divisional exposure technique, dividing the device region into smaller sections that can be exposed individually, allowing for the formation of damascene structures with varying widths and distances, including a wider intermediate portion between adjacent wirings, which can be manufactured using standard exposure apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional exposure apparatuses are used to expose the entire device region at once, then the exposure process is simple and fast, but the wiring cannot be miniaturized when dimensions exceed the maximum exposure region
Solution Approach 1:
The device region is divided into multiple sub-regions (first region, second region, third region) that are exposed separately in multiple exposure shots. This segmentation allows each sub-region to be within the maximum exposure region of the apparatus while achieving the overall miniaturization goal across the entire device.
Solution Approach 2:
The first exposure shot performs preliminary patterning on the first and third regions, creating a partial resist pattern. The second exposure shot then completes the patterning on the second region. This preliminary action enables the formation of fine features that would be impossible to achieve in a single exposure shot.
2Manufacturing precision
If the wiring width is reduced to achieve miniaturization, then the device density is improved, but the distance between adjacent wirings becomes difficult to control precisely
Solution Approach 1:
The intermediate portion of the wiring has a different width than the first and second portions, creating local variations in wire thickness. This local quality change allows the intermediate portion to serve as a buffer that maintains precise spacing control with adjacent wirings while still achieving miniaturization in the first and second portions.
3Manufacturing precision
If multiple exposure shots are used to expose the entire device region, then wiring miniaturization is achieved, but the manufacturing time and process complexity increase
Solution Approach 1:
The exposure process is segmented into multiple shots covering different regions, allowing parallel processing of multiple areas. This segmentation enables miniaturization to be achieved across the entire device while managing the total exposure time through efficient regional division.
4Ease of manufacture
If the intermediate portion width is increased to facilitate exposure, then the exposure process becomes easier, but the wiring uniformity decreases
Solution Approach 1:
The wiring structure intentionally incorporates local quality variations with a wider intermediate portion and narrower first and second portions. This design makes the exposure process easier by providing a broader intermediate region for pattern transfer, while the narrower portions maintain wiring uniformity and prevent line noise in the final structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective miniaturization of wiring, improving uniformity and sensitivity in semiconductor devices, while overcoming the limitations of conventional exposure apparatuses by allowing for precise patterning and reducing line noise.
Implementation Method 1
exposing a photoresist film of positive type provided on the insulator film, developing the photoresist film to form a resist pattern from the photoresist film
Data Source
AI summary
A semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein the first wiring includes, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion located between the first portion and the second portion, and wherein a width of the third portion is larger than each of a width of the first portion and a width of the second portion.