Damascene Wiring Patterning for Semiconductor Integration
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Solution Overview
Problem
As semiconductor devices undergo increased integration, the design rule for their components is reduced, posing challenges in patterning limitations due to the resolution limits of photolithographic processes, leading to issues like electrical shorts and burying failures in damascene wiring formation.
Innovation Solution
A method involving sequential formation of damascene mask layers and mask layers on a substrate, with etching processes to create overlapping damascene patterns and trenches, using carbon-containing layers and silicon oxynitride, to form damascene wiring with a flat bottom and prevent over-etching, ensuring proper connection and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processes are used for patterning, then manufacturing process is simple, but patterning precision deteriorates due to resolution limits
Solution Approach 1:
The patent divides the single photolithography step into multiple sequential steps: first photolithography to form initial mask pattern, then damascene processes with additional mask layers (second and third mask layers) to achieve finer patterning. This segmentation allows overcoming the resolution limit of single photolithography while maintaining manageable process complexity through systematic breakdown.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional damascene structure formation by adding vertical mask layers and performing selective etching. The first, second, and third damascene mask layers create overlapping patterns in the vertical dimension, enabling precise control of trench geometry and wiring pitch that cannot be achieved with conventional single-layer photolithography.
2Productivity
If design rule is reduced for increased integration, then device integration increases, but patterning reliability deteriorates
Solution Approach 1:
The patent performs preliminary actions by forming the first mask layer pattern with precise dimensions before subsequent etching steps. The second and third mask layers are prepared in advance with designed overlaps to ensure accurate trench formation. This preliminary patterning with multiple mask layers establishes a reliable foundation for creating fine-pitch damascene wiring structures, preventing pattern defects even at reduced design rules.
Solution Approach 2:
The patent introduces intermediate mask layers (second and third damascene mask layers) as mediators between the initial photolithography pattern and the final trench structure. These intermediate layers act as buffers that refine the pattern progressively, ensuring high reliability in trench formation at reduced pitch by providing multiple opportunities for pattern correction and optimization.
3Reliability
If conventional damascene wiring formation is used, then process is simple, but electrical shorts and burying failures occur
Solution Approach 1:
The patent applies local quality by making the third damascene mask layer selectively removable in specific regions. The third mask layer is retained in first regions (where wiring should continue) and removed in second regions (where trenches should be formed). This spatially differentiated treatment of the mask layer prevents electrical shorts by maintaining wiring continuity where needed while enabling trench formation where isolation is required, eliminating burying failures through precise local control.
Solution Approach 2:
The patent introduces dynamic adaptability in the damascene process by making the third mask layer's retention or removal dependent on the specific region being processed. This dynamic approach allows the same mask layer structure to serve different functions in different locations, enabling the process to adapt to varying wiring density requirements and prevent both electrical shorts in dense regions and burying failures in isolated regions.
Data Source
AI summary
A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.