DAPU CAM Index Coalescing for Autonomous Perception
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit architectures, particularly GPUs, lack the necessary processing capabilities to handle complex machine learning algorithms and real-time sensor signal processing for autonomous robotics and vehicles, leading to inefficiencies in perception processing tasks.
Innovation Solution
A dense algorithm processing unit (DAPU) with a mesh architecture that includes an array of processing cores, border cores, and a content addressable memory (CAM), enabling efficient in-memory computing and data movement through a predetermined data flow schedule, which optimizes the processing of perception algorithms and sensor data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional GPU architectures are used for sensor processing, then basic computation can be performed, but the processing capability for complex machine learning algorithms and real-time sensor signal processing is insufficient
Solution Approach 1:
The system segments processing tasks into two distinct units: a perception processing unit (PPU) dedicated to sensor data and machine learning algorithms, and a dense algorithm processing unit (DAPU) for other computations. This segmentation allows each unit to be optimized for its specific function, resolving the contradiction between processing capability and architecture complexity.
Solution Approach 2:
The PPU is designed as a universal processing unit that can handle multiple perception tasks including sensor signal processing, machine learning inference, and path planning through configurable neural network layers. This multi-functionality improves processing capability without requiring separate specialized hardware for each task.
2Productivity
If additional and/or disparate circuitry is assembled to a traditional GPU to handle perception processing needs, then processing capabilities are enhanced, but inefficiencies in performing computations including sensor signal processing occur
Solution Approach 1:
The patent merges the PPU and DAPU into a unified integrated circuit system with shared memory resources and coordinated data flow. This integration eliminates the inefficiencies of disparate circuitry by providing seamless data exchange and coordinated operation, while maintaining enhanced perception processing capabilities.
Solution Approach 2:
The system introduces a memory interface and data movement unit as intermediaries between the PPU and DAPU, facilitating efficient data exchange. This intermediary layer resolves operational inefficiencies by providing optimized data transfer paths and coordination mechanisms between the two processing units.
3Loss of time
If general purpose integrated circuits including CPUs and GPUs are used, then basic processing can be performed, but high performance and real-time computing of sensor signal data is not achieved
Solution Approach 1:
The PPU is pre-configured with neural network layer structures and processing pipelines optimized for real-time perception tasks. Data flows through pre-established processing stages including convolutional layers, activation functions, and pooling operations, enabling real-time processing without the overhead of dynamic configuration.
Solution Approach 2:
The system implements dynamic data flow paths within the PPU that can be reconfigured based on the specific neural network being executed. This dynamic adaptability allows the fixed hardware architecture to achieve high performance for various real-time processing tasks while managing complexity through structured flexibility.
Data Source
AI summary
A system and method for random access augmented flow-based processing within an integrated circuit includes computing, by a plurality of distinct processing cores, a plurality of linear indices and associated valid bits; propagating the plurality of linear indices in a predetermined manner to a plurality of columns of first-in, first-out buffers; loading, from the FIFO buffers, the plurality of linear indices to a content addressable memory; at the CAM: coalescing redundant linear indices in each of the plurality of FIFO buffers; performing lookups for a plurality of memory addresses based on the plurality of linear indices; collecting at a read data buffer a plurality of distinct pieces of data from one of an on-chip memory based on the plurality of memory addresses; reading the plurality of distinct pieces of data from the read data buffer; and propagating the plurality of distinct pieces of data into the processing cores.