CMOS Image Sensor Dark ADC Timing Offset for Faster Readout
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Solution Overview
Problem
Current image sensor systems require significant ADC time for dark signals, which limits frame rate and increases power consumption and noise, especially due to the need for special analog circuits in analog domain subtraction methods.
Innovation Solution
The proposed solution involves adjusting the start timing of the second ADC conversion based on a timing offset determined from the dark signal, reducing ADC time for dark signals without affecting image quality, and implementing this in CMOS image sensors using readout circuitry and logic circuitry that includes a phased locked loop, clock divider, and ramp generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dark signal subtraction is performed in the analog domain using special analog circuits, then ADC time for dark signals is eliminated, but device complexity increases and power consumption increases
Solution Approach 1:
The patent replaces the mechanical/electrical analog circuit system with a digital signal processing system. Instead of using special analog circuits to subtract dark signals before ADC conversion, the invention uses digital signal processing to achieve the same result after ADC conversion, thereby eliminating the need for complex analog circuits while maintaining the benefit of reduced ADC time for dark signals.
Solution Approach 2:
The patent changes the timing parameters of the ADC conversion process. By adjusting the ADC conversion timing to occur after dark signal subtraction in the digital domain, the system eliminates the need for separate dark signal ADC conversion, thereby reducing the overall ADC time dedicated to dark signals without requiring additional analog circuitry.
2Loss of time
If dark signal subtraction is performed in the analog domain, then ADC time for dark signals is eliminated, but power consumption increases
Solution Approach 1:
The patent substitutes power-hungry analog circuit operations with more energy-efficient digital signal processing operations. The digital domain subtraction requires less power than maintaining and operating special analog subtraction circuits, especially at high conversion rates, thereby reducing overall power consumption while achieving the same time savings.
3Loss of time
If dark signal subtraction is performed in the analog domain, then ADC time for dark signals is eliminated, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces analog circuit operations with digital signal processing, which is inherently more precise and less sensitive to manufacturing variations. Digital logic and arithmetic operations have well-defined thresholds and can be manufactured with standard precision, whereas analog circuits require high-precision component matching and layout to achieve accurate subtraction, making the digital approach more manufacturable.
4Productivity
If frame rate is increased, then productivity improves, but ADC time for dark signals becomes a limiting factor
Solution Approach 1:
The patent performs dark signal subtraction in the digital domain after ADC conversion, which allows the ADC to operate continuously at high rates without being interrupted by separate dark signal conversion cycles. This preliminary digital processing approach enables higher frame rates because the ADC can maintain its maximum conversion rate while the dark signal correction is handled efficiently in the digital domain.
Solution Approach 2:
The patent enables continuous ADC operation by eliminating the need to pause or slow down the ADC for separate dark signal conversions. The ADC continuously converts all pixel signals including dark signals at full rate, and the dark signal subtraction is performed continuously in the digital domain, maintaining uninterrupted high-speed operation that enables higher frame rates.
Data Source
AI summary
A method for reducing ADC time for dark signals starts with pixel array capturing image data of frames including first frame and second frame. Pixel array includes visible pixels and black pixels (OPB). Scanning circuitry then selects OPB of first frame to be readout. OPB generate a dark signal when selected by scanning circuitry. Column readout circuitry included in readout circuitry then acquires the dark signal of first frame and processes the dark signal based on a ramp signal received from ramp generator included in readout circuitry to generate dark ADC output. Readout circuitry then determines a ramp timing offset based on the dark signal of first frame. The ramp timing offset is then applied to the second frame, which includes generating by the ramp generator the ramp signal for a second frame that includes the ramp timing offset. Other embodiments are described.